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R
ST62T52B ST62T62B/E62B
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER AND EEPROM
s s s s s s s
s s s s
s
s
s
s s s
s s s
3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data Storage in Program Memory: User selectable size Data RAM: 128 bytes Data EEPROM: 64 bytes (none on ST62T52B) User Programmable Options 9 I/O pins, fully programmable as: - Input with pull-up resistor - Input without pull-up resistor - Input with interrupt generation - Open-drain or push-pull output - Analog Input 5 I/O lines can sink up to 20mA to drive LEDs or TRIACs directly 8-bit Timer/Counter with 7-bit programmable prescaler 8-bit Auto-reload Timer with 7-bit programmable prescaler (AR Timer) Digital Watchdog 8-bit A/D Converter with 4 analog inputs On-chip Clock oscillator can be driven by Quartz Crystal Ceramic resonator or RC network User configurable Power-on Reset One external Non-Maskable Interrupt ST626x-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port)
PDIP16
PSO16
CDIP16W
(See end of Datasheet for Ordering Information)
DEVICE SUMMARY
DEVICE ST62T52B ST62T62B ST62E62B 1836 EPROM
(Bytes)
OTP
(Bytes)
EEPROM 64 64
1836 1836
Rev. 2.4
April 1998
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Table of Contents
ST62T52B / ST62T62B/E62B . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.6 Data RAM/EEPROM Bank Register (DRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 . EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 13 14 14
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 16 3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 19 19 19 21
3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . 4.1.2 Safe I/O State Switching Sequence . . . . . 4.1.3 ARTimer alternate functions . . . . . . . . . . 4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ....... . . . 68 . . .. ....... ....... 25 26 27 27 29 29 29 30 31 31 32 33 35 36
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Table of Contents
4.2.1 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 AR Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 37 38 39 39 39 43 45
4.4.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.8 ARTIMER ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ST62P52B / ST62P62B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.2.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ST6252B / ST6262B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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ST62T52B ST62T62B/E62B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST62T52B and ST62T62B devices is low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a common core is surrounded by a number of on-chip peripherals. The ST62E62B is the erasable EPROM version of the ST62T62B device, which may be used to emulate the ST62T52B and ST62T62B devices as well as the ST6252B and ST6262B ROM devices. OTP and EPROM devices are functionally identical. The ROM based versions offer the same functionality selecting as ROM options the options deFigure 1. Block Diagram fined in the programmable option byte of the OTP/EPROM versions. OTP devices offer all the advantages of user programmability at low cost, which make them the ideal choice in a wide range of applications where frequent code changes, multiple code versions or last minute programmability are required. These compact low-cost devices feature a Timer comprising an 8-bit counter and a 7-bit programmable prescaler, an 8-bit Auto-Reload Timer, EEPROM data capability (except ST62T52B), an 8-bit A/D Converter with 4 analog inputs and a Digital Watchdog timer, making them well suited for a wide range of automotive, appliance and industrial applications.
8-BIT A/D CONVERTER TEST/VPP TEST
PORT A
PA4..PA5 / Ain PB0, PB2..PB3 / 20 mA Sink PB6 / ARTimin / 20 mA Sink PB7 / ARTimout / 20 mA Sink PC2..PC3 / Ain
PORT B NMI INTERRUPT DATA ROM USER SELECTABLE DATA RAM
1836 bytes OTP (ST62T52B, T62B) 1836 bytes EPROM (ST62E62B) 128 Bytes
PORT C
PROGRAM MEMORY AUTORELOAD TIMER
DATA EEPROM
64 Bytes (ST62T62B/E62B)
TIMER
PC STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 POWER SUPPLY 8 BIT CORE DIGITAL WATCHDOG
OSCILLATOR
RESET
VDD VSS
OSCin OSCout
RESET
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ST62T52B ST62T62B/E62B
1.2 PIN DESCRIPTIONS VDD and VSS. Power is supplied to the MCU via these two pins. VDD is the power connection and VSS is the ground connection. OSCin and OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins. The OSCin pin is the input pin, the OSCout pin is the output pin. RESET. The active-low RESET pin is used to restart the microcontroller. TEST/VPP. The TEST must be held at VSS for normal operation. If TEST pin is connected to a +12.5V level during the reset phase, the EPROM/OTP programming Mode is entered. NMI. The NMI pin provides the capability for asynchronous interruption, by applying an external non maskable interrupt to the MCU. The NMI input is falling edge sensitive. It is provided with an onchip pullup resistor and Schmitt trigger characteristics. PA4-PA5. These 2 lines are organized as one I/O port (A). Each line may be configured under software control as inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pull outputs, analog inputs for the A/D converter. PB0, PB2-PB3, PB6-PB7. These 5 lines are organized as one I/O port (B). Each line may be configured under software control as inputs with or without internal pull-up resistors, interrupt generating inputs with pull-up resistors, open-drain or push-pull outputs. PB6/ARTIMin and PB7/ARTIMout are either Port B I/O bits or the Input and Output pins of the ARTimer. Reset state of PB2-PB3 pins can be defined by option either with pull-up or high impedance. PB0, PB2-PB3, PB6-PB7 scan also sink 20mA for direct LED driving. PC2-PC3. These 2 lines are organized as one I/O port (C). Each line may be configured under software control as input with or without internal pullup resistor, interrupt generating input with pull-up resistor, analog input for the A/D converter, opendrain or push-pull output. Figure 2. ST62T52B, E62B and T62B Pin Configuration
PB0 VPP/TEST PB2 PB3 ARTIMin/PB6 ARTIMout/PB7 VDD VSS
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
PC2/Ain PC3/Ain NMI RESET OSCout OSCin PA5/Ain PA4/Ain
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1.3 MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Figure 3. Memory Addressing Diagram Briefly, Program space contains user program code in OTP and user vectors; Data space contains user data in RAM and in OTP, and Stack space accommodates six levels of stack for subroutine and interrupt service routine nesting.
PROGRAM SPACE
DATA SPACE
0000h
000h RAM / EEPROM BANKING AREA 0-63 03Fh 040h DATA READ-ONLY MEMORY WINDOW 07Fh 080h 081h 082h 083h 084h 0C0h X REGISTER Y REGISTER V REGISTER W REGISTER RAM DATA READ-ONLY MEMORY WINDOW SELECT DATA RAM BANK SELECT ACCUMULATOR
PROGRAM MEMORY
0FF0h INTERRUPT & RESET VECTORS 0FFFh 0FFh
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MEMORY MAP (Cont'd) 1.3.2 Program Space Program Space comprises the instructions to be executed, the data required for immediate addressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the 12-bit Program Counter register (PC register). 1.3.2.1 Program Memory Protection The Program Memory in OTP or EPROM devices can be protected against external readout of memory by selecting the READOUT PROTECTION option in the option byte. In the EPROM parts, READOUT PROTECTION option can be disactivated only by U.V. erasure that also results into the whole EPROM context erasure. Note: Once the Readout Protection is activated, it is no longer possible, even for SGS-THOMSON, to gain access to the OTP contents. Returned parts with a protection set can therefore not be accepted. Figure 4. ST62T52B/T62B Program Memory Map
0000h
RESERVED*
087Fh 0880h
USER PROGRAM MEMORY 1836 BYTES (OTP/EPROM)
0F9Fh 0FA0h 0FEFh 0FF0h 0FF7h 0FF8h 0FFBh 0FFCh 0FFDh 0FFEh 0FFFh
RESERVED* INTERRUPT VECTORS RESERVED NMI VECTOR USER RESET VECTOR
(*) Reserved areas should be filled with 0FFh
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ST62T52B ST62T62B/E62B
MEMORY MAP (Cont'd) 1.3.3 Data Space Data Space accommodates all the data necessary for processing the user program. This space comprises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in OTP/EPROM. 1.3.3.1 Data ROM All read-only data is physically stored in program memory, which also accommodates the Program Space. The program memory consequently contains the program code to be executed, as well as the constants and look-up tables required by the application. The Data Space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in OTP/EPROM. 1.3.3.2 Data RAM/EEPROM In ST62T52B, T62B and ST62E62B devices, the data space includes 60 bytes of RAM, the accumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port registers, the peripheral data and control registers, the interrupt option register and the Data ROM Window register (DRW register). Additional RAM and EEPROM pages can also be addressed using banks of 64 bytes located between addresses 00h and 3Fh. 1.3.4 Stack Space Stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents. Table 1. Additional RAM / EEPROM Banks
Device ST62T52B ST62T62B RAM 1 x 64 bytes 1 x 64 bytes EEPROM 1 x 64 bytes
Table 2. ST62T52B, T62B and ST62E62B Data Memory Space
RAM / EEPROM banks 000h 03Fh 040h 07Fh 080h 081h 082h 083h 084h 0BFh 0C0h 0C1h 0C2h 0C3h 0C4h 0C5h 0C6h 0C7h 0C8h* 0C9h* 0CAh 0CBh 0CCh 0CDh 0CEh 0CFh 0D0h 0D1h 0D2h 0D3h 0D4h 0D5h 0D6h 0D7h 0D8h 0D9h 0DAh 0DBh 0DCh* 0DDh 0DEh 0E7h 0E8h* 0E9h 0EAh 0EBh 0FEh 0FFh
DATA ROM WINDOW AREA X REGISTER Y REGISTER V REGISTER W REGISTER DATA RAM 60 BYTES PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER RESERVED PORT A DIRECTION REGISTER PORT B DIRECTION REGISTER PORT C DIRECTION REGISTER RESERVED INTERRUPT OPTION REGISTER DATA ROM WINDOW REGISTER RESERVED PORT A OPTION REGISTER PORT B OPTION REGISTER PORT C OPTION REGISTER RESERVED A/D DATA REGISTER A/D CONTROL REGISTER TIMER PRESCALER REGISTER TIMER COUNTER REGISTER TIMER STATUS CONTROL REGISTER AR TIMER MODE CONTROL REGISTER AR TIMER STATUS/CONTROL REGISTER1 AR TIMER STATUS/CONTROL REGISTER2 WATCHDOG REGISTER AR TIMER RELOAD/CAPTURE REGISTER AR TIMER COMPARE REGISTER AR TIMER LOAD REGISTER OSCILLATOR CONTROL REGISTER MISCELLANEOUS RESERVED DATA RAM/EEPROM REGISTER RESERVED EEPROM CONTROL REGISTER RESERVED ACCUMULATOR
* WRITE ONLY REGISTER
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ST62T52B ST62T62B/E62B
MEMORY MAP (Cont'd) 1.3.5 Data Window Register (DWR) The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes located anywhere in program memory, between address 0000h and 0FFFh (top memory address depends on the specific device). All the program memory can therefore be used to store either instructions or read-only data. Indeed, the window can be moved in steps of 64 bytes along the program memory by writing the appropriate code in the Data Window Register (DWR). The DWR can be addressed like any RAM location in the Data Space, it is however a write-only register and therefore cannot be accessed using single-bit operations. This register is used to position the 64-byte read-only data window (from address 40h to address 7Fh of the Data space) in program memory in 64-byte steps. The effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the register address given in the instruction (as least significant bits) and the content of the DWR register (as most significant bits), as illustrated in Figure 5 below. For instance, when addressing location 0040h of the Data Space, with 0 loaded in the DWR register, the physical location addressed in program memory is 00h. The DWR register is not cleared on reset, therefore it must be written to prior to the first access to the Data read-only memory window area.
Data Window Register (DWR) Address: 0C9h
7 -
--
Write Only
0
DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
Bits 6, 7 = Not used. Bit 5-0 = DWR5-DWR0: Data read-only memory Window Register Bits. These are the Data readonly memory Window bits that correspond to the upper bits of the data read-only memory space. Caution: This register is undefined on reset. Neither read nor single bit instructions may be used to address this register. Note: Care is required when handling the DWR register as it is write only. For this reason, the DWR contents should not be changed while executing an interrupt service routine, as the service routine cannot save and then restore the register's previous contents. If it is impossible to avoid writing to the DWR during the interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to the DWR, it must also write to the image register. The image register must be written first so that, if an interrupt occurs between the two instructions, the DWR is not affected.
Figure 5. Data read-only memory Window Memory Addressing
13 12 DATA ROM WINDOW REGISTER 7 6 CONTENTS (DWR) 11 10 9 5 4 3 8 2 7 1 6 0 5 0 1 4 3 2 1 5 4 3 2 1 0 PROGRAM SPACE ADDRESS READ 0 DATA SPACE ADDRESS : 40h-7Fh IN INSTRUCTION
Example: DWR=28h 1 0 1 0 0 0 0 1 0 1 1 0 0 1 DATA SPACE ADDRESS : 59h
ROM ADDRESS:A19h
1
0
1
0
0
0
0
1
1
0
0
1 VR01573C
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MEMORY MAP (Cont'd) 1.3.6 Data RAM/EEPROM (DRBR) Address: E8h -- Write only
7 DRBR 4 -
Bank
Register
0 DRBR 0
Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page 2. Bit 1-3. Not used Bit 0. DRBR0. This bit, when set, selects EEPROM page 0. The selection of the bank is made by programming the Data RAM Bank Switch register (DRBR register) located at address E8h of the Data Space according to Table 1. No more than one bank should be set at a time. The DRBR register can be addressed like a RAM Data Space at the address E8h; nevertheless it is a write only register that cannot be accessed with single-bit operations. This register is used to select the desired 64-byte RAM bank of the Data Space. The number of banks has to be loaded in the DRBR register and the instruction has to point to the selected location as if it was in bank 0 (from 00h address to 3Fh address). This register is not cleared during the MCU initialization, therefore it must be written before the first access to the Data Space bank region. Refer to
the Data Space description for additional information. The DRBR register is not modified when an interrupt or a subroutine occurs. Notes : Care is required when handling the DRBR register as it is write only. For this reason, it is not allowed to change the DRBR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to DRBR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected. In DRBR Register, only 1 bit must be set. Otherwise two or more pages are enabled in parallel, producing errors. Table 3. Data RAM Bank Register Set-up
DRBR 00 01 02 08 10h other ST62T52B None Not available Not Available Not available RAM Page 2 Reserved ST62T62B None EEPROM page 0 Not Available Not available RAM Page 2 Reserved
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MEMORY MAP (Cont'd) 1.3.7 EEPROM Description EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh is paged as described in Table 4 . Row Arrangement for Parallel Writing of EEPROM Locations. EEPROM locations are accessed directly by addressing these paged sections of data space. The EEPROM does not require dedicated instructions for read or write access. Once selected via the Data RAM Bank Register, the active EEPROM page is controlled by the EEPROM Control Register (EECTL), which is described below. Bit E20FF of the EECTL register must be reset prior to any write or read access to the EEPROM. If no bank has been selected, or if E2OFF is set, any access is meaningless. Programming must be enabled by setting the E2ENA bit of the EECTL register. The E2BUSY bit of the EECTL register is set when the EEPROM is performing a programming cycle. Any access to the EEPROM when E2BUSY is set is meaningless. Provided E2OFF and E2BUSY are reset, an EEPROM location is read just like any other data location, also in terms of access time. Writing to the EEPROM may be carried out in two modes: Byte Mode (BMODE) and Parallel Mode
(PMODE). In BMODE, one byte is accessed at a time, while in PMODE up to 8 bytes in the same row are programmed simultaneously (with consequent speed and power consumption advantages, the latter being particularly important in battery powered circuits). General Notes: Data should be written directly to the intended address in EEPROM space. There is no buffer memory between data RAM and the EEPROM space. When the EEPROM is busy (E2BUSY = "1") EECTL cannot be accessed in write mode, it is only possible to read the status of E2BUSY. This implies that as long as the EEPROM is busy, it is not possible to change the status of the EEPROM Control Register. EECTL bits 4 and 5 are reserved and must never be set. Care is required when dealing with the EECTL register, as some bits are write only. For this reason, the EECTL contents must not be altered while executing an interrupt service routine. If it is impossible to avoid writing to this register within an interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to EECTL it must also write to the image register. The image register must be written to first so that, if an interrupt occurs between the two instructions, the EECTL will not be affected.
Table 4. . Row Arrangement for Parallel Writing of EEPROM Locations
Dataspace addresses. Banks 0 and 1. Byte ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 0 1 2 3 4 5 6 7 38h-3Fh 30h-37h 28h-2Fh 20h-27h 18h-1Fh 10h-17h 08h-0Fh 00h-07h Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode. The number of available 64-byte banks (1 or 2) is device dependent.
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MEMORY MAP (Cont'd) Additional Notes on Parallel Mode: If the user wishes to perform parallel programming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be addressed in write mode, the ROW address will be latched and it will be possible to change it only at the end of the programming cycle, or by resetting E2PAR2 without programming the EEPROM. After the ROW address is latched, the MCU can only "see" the selected EEPROM row and any attempt to write or read other rows will produce errors. The EEPROM should not be read while E2PAR2 is set. As soon as the E2PAR2 bit is set, the 8 volatile ROW latches are cleared. From this moment on, the user can load data in all or in part of the ROW. Setting E2PAR1 will modify the EEPROM registers corresponding to the ROW latches accessed after E2PAR2. For example, if the software sets E2PAR2 and accesses the EEPROM by writing to addresses 18h, 1Ah and 1Bh, and then sets E2PAR1, these three registers will be modified simultaneously; the remaining bytes in the row will be unaffected. Note that E2PAR2 is internally reset at the end of the programming cycle. This implies that the user must set the E2PAR2 bit between two parallel programming cycles. Note that if the user tries to set E2PAR1 while E2PAR2 is not set, there will be no programming cycle and the E2PAR1 bit will be unaffected. Consequently, the E2PAR1 bit cannot be set if E2ENA is low. The E2PAR1 bit can be set by the user, only if the E2ENA and E2PAR2 bits are also set.
EEPROM Control Register (EECTL) Address: EAh -- Read/Write Reset status: 00h
7 D7 E2O FF D5 D4 E2PA R1 E2PA R2 0 E2BU E2E SY NA
Bit 7 = D7: Unused. Bit 6 = E2OFF: Stand-by Enable Bit. WRITE ONLY. If this bit is set the EEPROM is disabled (any access will be meaningless) and the power consumption of the EEPROM is reduced to its lowest value. Bit 5-4 = D5-D4: Reserved. MUST be kept reset. Bit 3 = E2PAR1: Parallel Start Bit. WRITE ONLY. Once in Parallel Mode, as soon as the user software sets the E2PAR1 bit, parallel writing of the 8 adjacent registers will start. This bit is internally reset at the end of the programming procedure. Note that less than 8 bytes can be written if required, the undefined bytes being unaffected by the parallel programming cycle; this is explained in greater detail in the Additional Notes on Parallel Mode overleaf. Bit 2 = E2PAR2: Parallel Mode En. Bit. WRITE ONLY. This bit must be set by the user program in order to perform parallel programming. If E2PAR2 is set and the parallel start bit (E2PAR1) is reset, up to 8 adjacent bytes can be written simultaneously. These 8 adjacent bytes are considered as a row, whose address lines A7, A6, A5, A4, A3 are fixed while A2, A1 and A0 are the changing bits, as illustrated in Table 4. E2PAR2 is automatically reset at the end of any parallel programming procedure. It can be reset by the user software before starting the programming procedure, thus leaving the EEPROM registers unchanged. Bit 1 = E2BUSY: EEPROM Busy Bit. READ ONLY. This bit is automatically set by the EEPROM control logic when the EEPROM is in programming mode. The user program should test it before any EEPROM read or write operation; any attempt to access the EEPROM while the busy bit is set will be aborted and the writing procedure in progress will be completed. Bit 0 = E2ENA: EEPROM Enable Bit. WRITE ONLY. This bit enables programming of the EEPROM cells. It must be set before any write to the EEPROM register. Any attempt to write to the EEPROM when E2ENA is low is meaningless and will not trigger a write cycle.
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1.4 PROGRAMMING MODES 1.4.1 Option Byte The Option Byte allows configuration capability to the MCUs. Option byte's content is automatically read, and the selected options enabled, when the chip reset is activated. It can only be accessed during the programming mode. This access is made either automatically (copy from a master device) or by selecting the OPTION BYTE PROGRAMMING mode of the programmer. The option byte is located in a non-user map. No address has to be specified. EPROM Code Option Byte
7 PRO- EXTC- PB2-3 TECT NTL PULL WDACT DELAY OSCIL 0 -
the oscillator, it is of 32768 cycles when DELAY is high. OSCIL. When this bit is low, the oscillator must be controlled by a quartz crystal, a ceramic resonator or an external frequency. When it is high, the oscillator must be controlled by an RC network, with only the resistor having to be externally provided. D0. Reserved. Must be cleared to zero. The Option byte is written during programming either by using the PC menu (PC driven Mode) or automatically (stand-alone mode) 1.4.2 Program Memory EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/VPP pin. The programming flow of the ST62T62B is described in the User Manual of the EPROM Programming Board. The MCUs can be programmed with the ST62E6xB EPROM programming tools available from SGS-THOMSON. Table 5. ST62T52B/T62B Program Memory Map
Device Address 0000h-087Fh 0880h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh Description Reserved User ROM Reserved Interrupt Vectors Reserved NMI Interrupt Vector Reset Vector
PROTECT. This bit allows the protection of the software contents against piracy. When the bit PROTECT is set high, readout of the OTP contents is prevented by hardware. No programming equipment is able to gain access to the user program. When this bit is low, the user program can be read. EXTCNTL. This bit selects the External STOP Mode capability. When EXTCNTL is high, pin NMI controls if the STOP mode can be accessed when the watchdog is active. When EXTCNTL is low, the STOP instruction is processed as a WAIT as soon as the watchdog is active. PB2-3 PULL. When set this bit removes pull-up at reset on PB2-PB3 pins. When cleared PB2-PB3 pins have an internal pull-up resistor at reset. D4. Reserved. Must be cleared to zero. WDACT. This bit controls the watchdog activation. When it is high, hardware activation is selected. The software activation is selected when WDACT is low. DELAY. This bit enables the selection of the delay internally generated after pin RESET is released. When DELAY is low, the delay is 2048 cycles of
Note: OTP/EPROM devices can be programmed with the development tools available from SGS-THOMSON (ST62E6X-EPB or ST626X-KIT). 1.4.3 . EEPROM Data Memory EEPROM data pages are supplied in the virgin state FFh. Partial or total programming of EEPROM data memory can be performed either through the application software or through an external programmer. Any SGS-THOMSON tool used for the program memory (OTP/EPROM) can also be used to program the EEPROM data memory.
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2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 6; the controller being externally linked to both the Reset and Oscillator circuits, while the core is linked to the dedicated on-chip peripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers. 2.2 CPU REGISTERS The ST6 Family CPU core features six registers and three pairs of flags available to the programmer. These are described in the following paragraphs. Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator can be addressed in Data space as a RAM location at address FFh. Thus the ST6 can manipulate the accumulator just like any other register in Data space. Figure 6ST6 Core Block Diagram
0,01 TO 8MHz RESET OSCin OSCout
Indirect Registers (X, Y). These two indirect registers are used as pointers to memory locations in Data space. They are used in the register-indirect addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h (X) and 81h (Y). They can also be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST6 instruction set can use the indirect registers as any other register of the data space. Short Direct Registers (V, W). These two registers are used to save a byte in short direct addressing mode. They can be addressed in Data space as RAM locations at addresses 82h (V) and 83h (W). They can also be accessed using the direct and bit direct addressing modes. Thus, the ST6 instruction set can use the short direct registers as any other register of the data space. Program Counter (PC). The program counter is a 12-bit register which contains the address of the next ROM location to be processed by the core. This ROM location may be an opcode, an operand, or the address of an operand. The 12-bit length allows the direct addressing of 4096 bytes in Program space.
INTERRUPTS CONTROLLER DATA SPACE
OPCODE
FLAG VALUES
CONTROL SIGNALS 2 ADDRESS/READ LINE
DATA RAM/EEPROM
PROGRAM ROM/EPROM ADDRESS 256 DECODER A-DATA B-DATA
DATA ROM/EPROM DEDICATIONS ACCUMULATOR
12
Program Counter and 6 LAYER STACK
FLAGS ALU RESULTS TO DATA SPACE (WRITE LINE) VR01811
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CPU REGISTERS (Cont'd) However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register. The PC value is incremented after reading the address of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC. The program counter can be changed in the following ways: - JP (Jump) instructionPC=Jump address - CALL instructionPC= Call address - Relative Branch Instruction.PC= PC +/- offset - Interrupt PC=Interrupt vector - ResetPC= Reset vector - RET & RETI instructionsPC= Pop (stack) - Normal instructionPC= PC + 1 Flags (C, Z). The ST6 CPU includes three pairs of flags (Carry and Zero), each pair being associated with one of the three normal modes of operation: Normal mode, Interrupt mode and Non Maskable Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used in the Non Maskable Interrupt mode (CNMI, ZNMI). The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable Interrupt) is generated, the ST6 CPU uses the Interrupt flags (resp. the NMI flags) instead of the Normal flags. When the RETI instruction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context switching and thus retain their status. The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction; it also participates in the rotate left instruction. The Zero flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared. Switching between the three sets of flags is performed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags. Stack. The ST6 CPU includes a true LIFO hardware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the PC is shifted into the first level (the original contents of the sixth stack level are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is popped back into the previous level. Since the accumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine. The stack will remain in its "deepest" position if more than 6 nested calls or interrupts are executed, and consequently the last return address will be lost. It will also remain in its highest position if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed. Figure 7ST6 CPU Programming Mode
l
INDEX REGISTER
b7 b7 b7 b7 b7
X REG. POINTER Y REG. POINTER V REGISTER W REGISTER ACCUMULATOR
b0 SHORT DIRECT ADDRESSING MODE b0 b0 b0 b0 b0
b11
PROGRAM COUNTER
SIX LEVELS STACK REGISTER
NORMAL FLAGS INTERRUPT FLAGS NMI FLAGS
C C C
Z Z Z VA000423
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3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suitable ceramic resonator, or with an external resistor (R NET). Figure 8. illustrates various possible oscillator configurations using an external crystal or ceramic resonator, an external clock input, an external resistor (R NET). CL1 an CL2 should have a capacitance in the range 12 to 22 pF for an oscillator frequency in the 4-8 MHz range. A programmable divider is provided in order to adjust the internal clock of the MCU to the best power consumption and performance trade-off. The internal MCU clock frequency (fINT) drives directly the AR TIMER while it is divided by 12 to drive the TIMER, the A/D converter and the Watchdog timer, and by 13 to drive the CPU core, as may be seen in Figure 9.. With an 8 MHz oscillator frequency, the fastest machine cycle is therefore 1.625s. A machine cycle is the smallest unit of time needed to execute any operation (for instance, to increment the Program Counter). An instruction may require two, four, or five machine cycles for execution. 3.1.1 Main Oscillator The oscillator configuration may be specified by selecting the appropriate option. When the CRYSTAL/RESONATOR option is selected, it must be used with a quartz crystal, a ceramic resonator or an external signal provided on the OSCin pin. When the RC NETWORK option is selected, the system clock is generated by an external resistor. Figure 8. Oscillator Configurations
CRYSTAL/RESONATOR CLOCK CRYSTAL/RESONATOR option
ST6xxx
OSCin
OSCout
CL1n
CL2
EXTERNAL CLOCK CRYSTAL/RESONATOR option
ST6xxx
OSCin
OSCout NC
RC NETWORK RC NETWORK option
ST6xxx
OSCin NC
OSCout
RNET
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CLOCK SYSTEM (Cont'd) Oscillator Control Registers Address: DCh -- Write only
7 OSCR OSCR 3 2 RS1 0 RS0
Bit 7-4. These bits are not used. Bit 3. Reserved. Cleared at Reset. THIS BIT MUST BE SET TO 1 BY USER PROGRAM to achieve lowest power consumption. Bit 2. Reserved. Must be kept low. RS1-RS0. These bits select the division ratio of the Oscillator Divider in order to generate the internal frequency. The following selctions are available:
RS1 0 0 1 1 RS0 0 1 0 1 Division Ratio 1 2 4 4
Note: Care is required when handling the OSCR register as some bits are write only. For this reason, it is not allowed to change the OSCR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to OSCR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the OSCR is not affected.
Figure 9. Clock Circuit Block Diagram
fOSC OSCin fOSC POR
: 13
Core
Timer
MAIN OSCILLATOR
OSCILLATOR DIVIDER
fINT
: 12
Watchdog ADC
OSCout RS0, RS1
:1
AR Timer
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3.2 RESETS The MCU can be reset in three ways: - by the external Reset input being pulled low; - by Power-on Reset; - by the digital Watchdog peripheral timing out. 3.2.1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required. The RESET pin may be pulled low in RUN, WAIT or STOP mode. This input can be used to reset the MCU internal state and ensure a correct start-up procedure. The pin is active low and features a Schmitt trigger input. The internal Reset signal is generated by adding a delay to the external signal. Therefore even short pulses on the RESET pin are acceptable, provided VDD has completed its rising phase and that the oscillator is running correctly (normal RUN or WAIT modes). The MCU is kept in the Reset state as long as the RESET pin is held low. If RESET activation occurs in the RUN or WAIT modes, processing of the user program is stopped (RUN mode only), the Inputs and Outputs are configured as inputs with pull-up resistors and the main Oscillator is restarted. When the level on the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period. If RESET pin activation occurs in the STOP mode, the oscillator starts up and all Inputs and Outputs are configured as inputs with pull-up resistors. When the level of the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period. 3.2.2 Power-on Reset The function of the POR circuit consists in waking up the MCU at an appropriate stage during the power-on sequence. At the beginning of this sequence, the MCU is configured in the Reset state: all I/O ports are configured as inputs with pull-up resistors and no instruction is executed. When the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence is executed immediately following the internal delay. The internal delay is generated by an on-chip counter. The internal reset line is released 2048 internal clock cycles after release of the external reset. Notes: To ensure correct start-up, the user should take care that the reset signal is not released before the VDD level is sufficient to allow MCU operation at the chosen frequency (see Recommended Operating Conditions). A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. Figure 10. Reset and Interrupt Processing
RESET
NMI MASK SET INT LATCH CLEARED ( IF PRESENT )
SELECT NMI MODE FLAGS
PUT FFEH ON ADDRESS BUS
YES
IS RESET STILL PRESENT?
NO LOAD PC FROM RESET LOCATIONS FFE/FFF
FETCH INSTRUCTION VA000427
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RESETS (Cont'd) 3.2.3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. This, amongst other things, resets the watchdog counter. The MCU restarts just as though the Reset had been generated by the RESET pin, including the built-in stabilisation delay period. 3.2.4 Application Notes No external resistor is required between VDD and the Reset pin, thanks to the built-in pull-up device. The POR circuit operates dynamically, in that it triggers MCU initialization on detecting the rising edge of VDD. The typical threshold is in the region of 2 volts, but the actual value of the detected threshold depends on the way in which VDD rises. The POR circuit is NOT designed to supervise static, or slowly rising or falling VDD. 3.2.5 MCU Initialization Sequence When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (located in program ROM starting at address 0FFEh). A jump to the beginning of the user program must be coded at this address. Following a Figure 12. Reset Block Diagram
Reset, the Interrupt flag is automatically set, so that the CPU is in Non Maskable Interrupt mode; this prevents the initialisation routine from being interrupted. The initialisation routine should therefore be terminated by a RETI instruction, in order to revert to normal mode and enable interrupts. If no pending interrupt is present at the end of the initialisation routine, the MCU will continue by processing the instruction immediately following the RETI instruction. If, however, a pending interrupt is present, it will be serviced. Figure 11. Reset and Interrupt Processing
RESET
JP RESET VECTOR
JP:2 BYTES/4 CYCLES
INITIALIZATION ROUTINE RETI
RETI: 1 BYTE/2 CYCLES
VA00181
VDD fOSC CK
ST6 INTERNAL RESET COUNTER
300k
RESET 2.8k POWER ON RESET
RESET
RESET
WATCHDOG RESET
VA0200B
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RESETS (Cont'd) Table 6. Register Reset Status
Register Oscillator Control Register EEPROM Control Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status/Control AR TIMER Mode Control Register AR TIMER Status/Control 1 Register AR TIMER Status/Control 2Register AR TIMER Compare Register Miscellaneous Register X, Y, V, W, Register Accumulator Data RAM Data RAM Page REgister Data ROM Window Register EEPROM A/D Result Register AR TIMER Load Register AR TIMER Reload/Capture Register TIMER Counter Register TIMER Prescaler Register Watchdog Counter Register A/D Control Register Address(es) 0DCh 0EAh 0C0h to 0C2h 0C4h to 0C6h 0CCh to 0CEh 0C8h 0D4h 0D5h 0D6h 0D7h 0DAh 0DDh 080H TO 083H 0FFh 084h to 0BFh 0E8h 0C9h 00h to F3h 0D0h 0DBh 0D9h 0D3h 0D2h 0D8h 0D1h FFh 7Fh FEh 40h A/D in Standby Max count loaded Undefined As written if programmed 00h Status Comment fINT = fOSC; user must set bit3 to 1 EEPROM enabled (if available) I/O are Input with pull-up I/O are Input with pull-up I/O are Input with pull-up Interrupt disabled TIMER disabled AR TIMER stopped
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3.3 DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset by reloading the counter, and should therefore be written so that the counter is regularly reloaded while the user program runs correctly. In the event of a software mishap (usually caused by externally generated interference), the user program will no longer behave in its usual fashion and the timer register will thus not be reloaded periodically. Consequently the timer will decrement down to 00h and reset the MCU. In order to maximise the effectiveness of the Watchdog function, user software must be written with this concept in mind. Watchdog behaviour is governed by two options, known as "WATCHDOG ACTIVATION" (i.e. HARDWARE or SOFTWARE) and "EXTERNAL STOP MODE CONTROL" (see Table 7 Recommended Option Choices). In the SOFTWARE option, the Watchdog is disabled until bit C of the DWDR register has been set. When the Watchdog is disabled, low power Stop mode is available. Once activated, the Watchdog cannot be disabled, except by resetting the MCU. In the HARDWARE option, the Watchdog is permanently enabled. Since the oscillator will run continuously, low power mode is not available. The STOP instruction is interpreted as a WAIT instruction, and the Watchdog continues to countdown. However, when the EXTERNAL STOP MODE CONTROL option has been selected low power consumption may be achieved in Stop Mode. Execution of the STOP instruction is then governed by a secondary function associated with the NMI pin. If a STOP instruction is encountered when the NMI pin is low, it is interpreted as WAIT, as described above. If, however, the STOP instruction is encountered when the NMI pin is high, the Watchdog counter is frozen and the CPU enters STOP mode. When the MCU exits STOP mode (i.e. when an interrupt is generated), the Watchdog resumes its activity.
Table 7. Recommended Option Choices
Functions Required Stop Mode & Watchdog Stop Mode Watchdog Recommended Options "EXTERNAL STOP MODE" & "HARDWARE WATCHDOG" "SOFTWARE WATCHDOG" "HARDWARE WATCHDOG"
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DIGITAL WATCHDOG (Cont'd) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, location 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register (DWDR). This register is set to 0FEh on Reset: bit C is cleared to "0", which disables the Watchdog; the timer downcounter bits, T0 to T5, and the SR bit are all set to "1", thus selecting the longest Watchdog timer period. This time period can be set to the user's requirements by setting the appropriate value for bits T0 to T5 in the DWDR register. The SR bit must be set to "1", since it is this bit which generates the Reset signal when it changes to "0"; clearing this bit would generate an immediate Reset. It should be noted that the order of the bits in the DWDR register is inverted with respect to the associated bits in the down counter: bit 7 of the DWDR register corresponds, in fact, to T0 and bit 2 to T5. The user should bear in mind the fact that these bits are inverted and shifted with respect to the physical counter bits when writing to this register. The relationship between the DWDR register bits and the physical implementation of the Watchdog timer downcounter is illustrated in Figure 13.. Only the 6 most significant bits may be used to define the time period, since it is bit 6 which triggers the Reset when it changes to "0". This offers the user a choice of 64 timed periods ranging from 3,072 to 196,608 clock cycles (with an oscillator frequency of 8MHz, this is equivalent to timer periods ranging from 384 s to 24.576ms).
Figure 13. Watchdog Counter Control
D0 D1 WATCHDOG COUNTER D2 D3 D4 D5 D6 D7
C SR RESET T5 T4 T3 T2 T1 T0
WATCHDOG CONTROL REGISTER
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DIGITAL WATCHDOG (Cont'd) 3.3.1 Digital Watchdog Register (DWDR) Address: 0D8h -- Read/Write Reset status: 1111 1110b
7 T0 T1 T2 T3 T4 T5 SR 0 C
Bit 0 = C: Watchdog Control bit If the hardware option is selected, this bit is forced high and the user cannot change it (the Watchdog is always active). When the software option is selected, the Watchdog function is activated by setting bit C to 1, and cannot then be disabled (save by resetting the MCU). When C is kept low the counter can be used as a 7-bit timer. This bit is cleared to "0" on Reset. Bit 1 = SR: Software Reset bit This bit triggers a Reset when cleared. When C = "0" (Watchdog disabled) it is the MSB of the 7-bit timer. This bit is set to "1" on Reset. Bits 2-7 = T5-T0: Downcounter bits It should be noted that the register bits are reversed and shifted with respect to the physical counter: bit-7 (T0) is the LSB of the Watchdog downcounter and bit-2 (T5) is the MSB. These bits are set to "1" on Reset.
3.3.2 Application Notes The Watchdog plays an important supporting role in the high noise immunity of ST62xx devices, and should be used wherever possible. Watchdog related options should be selected on the basis of a trade-off between application security and STOP mode availability. When STOP mode is not required, hardware activation without EXTERNAL STOP MODE CONTROL should be preferred, as it provides maximum security, especially during power-on. When STOP mode is required, hardware activation and EXTERNAL STOP MODE CONTROL should be chosen. NMI should be high by default, to allow STOP mode to be entered when the MCU is idle. The NMI pin can be connected to an I/O line (see Figure 14.) to allow its state to be controlled by software. The I/O line can then be used to keep NMI low while Watchdog protection is required, or to avoid noise or key bounce. When no more processing is required, the I/O line is released and the device placed in STOP mode for lowest power consumption. When software activation is selected and the Watchdog is not activated, the downcounter may be used as a simple 7-bit timer (remember that the bits are in reverse order). The software activation option should be chosen only when the Watchdog counter is to be used as a timer. To ensure the Watchdog has not been unexpectedly activated, the following instructions should be executed within the first 27 instructions: jrr 0, WD, #+3 ldi WD, 0FDH
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DIGITAL WATCHDOG (Cont'd) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of 28 instructions are executed after activation, before the Watchdog can generate a Reset. Consequently, user software should load the watchdog counter within the first 27 instructions following Watchdog activation (software mode), or within the first 27 instructions executed following a Reset (hardware activation). It should be noted that when the GEN bit is low (interrupts disabled), the NMI interrupt is active but cannot cause a wake up from STOP/WAIT modes.
Figure 14. A typical circuit making use of the EXERNAL STOP MODE CONTROL feature
SWITCH NMI
I/O
VR02002
Figure 15. Digital Watchdog Block Diagram
RESET
Q RSFF R S
-2
7
DB1.7 LOAD SET
-2 8 SET
-12
DB0
8
OSCILLATOR CLOCK
WRITE RESET DATA BUS
VA00010
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3.4 INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is associated with a specific Interrupt Vector which contains a Jump instruction to the associated interrupt service routine. These vectors are located in Program space (see Table 8 Interrupt Vector Map). When an interrupt source generates an interrupt request, and interrupt processing is enabled, the PC register is loaded with the address of the interrupt vector (i.e. of the Jump instruction), which then causes a Jump to the relevant interrupt service routine, thus servicing the interrupt. Interrupt sources are linked to events either on external pins, or on chip peripherals. Several events can be ORed on the same interrupt source, and relevant flags are available to determine which event triggered the interrupt. The Non Maskable Interrupt request has the highest priority and can interrupt any interrupt routine at any time; the other four interrupts cannot interrupt each other. If more than one interrupt request is pending, these are processed by the processor core according to their priority level: source #1 has the higher priority while source #4 the lower. The priority of each interrupt source is fixed. Table 8. Interrupt Vector Map
Interrupt Source Interrupt source #0 Interrupt source #1 Interrupt source #2 Interrupt source #3 Interrupt source #4 Priority 1 2 3 4 5 Vector Address (FFCh-FFDh) (FF6h-FF7h) (FF4h-FF5h) (FF2h-FF3h) (FF0h-FF1h)
Interrupt request from the Non Maskable Interrupt source #0 is latched by a flip flop which is automatically reset by the core at the beginning of the non-maskable interrupt service routine. Interrupt request from source #1 can be configured either as edge or level sensitive by setting accordingly the LES bit of the Interrupt Option Register (IOR). Interrupt request from source #2 are always edge sensitive. The edge polarity can be configured by setting accordingly the ESB bit of the Interrupt Option Register (IOR). Interrupt request from sources #3 & #4 are level sensitive. In edge sensitive mode, a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started. So, the occurrence of an interrupt can be stored, until completion of the running interrupt routine before being processed. If several interrupt requests occurs before completion of the running interrupt routine, only the first request is stored. Storage of interrupt requests is not available in level sensitive mode. To be taken into account, the low level must be present on the interrupt pin when the MCU samples the line after instruction execution. At the end of every instruction, the MCU tests the interrupt lines: if there is an interrupt request the next instruction is not executed and the appropriate interrupt service routine is executed instead. Table 9. Interrupt Option Register Description
GEN SET CLEARED SET ESB CLEARED SET LES CLEARED OTHERS NOT USED Enable all interrupts Disable all interrupts Rising edge mode on interrupt source #2 Falling edge mode on interrupt source #2 Level-sensitive mode on interrupt source #1 Falling edge mode on interrupt source #1
3.4.1 Interrupt request All interrupt sources but the Non Maskable Interrupt source can be disabled by setting accordingly the GEN bit of the Interrupt Option Register (IOR). This GEN bit also defines if an interrupt source, including the Non Maskable Interrupt source, can restart the MCU from STOP/WAIT modes.
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IINTERRUPTS (Cont'd) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call procedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred. As a result, the user should save all Data space registers which may be used within the interrupt routines. There are separate sets of processor flags for normal, interrupt and non-maskable interrupt modes, which are automatically switched and so do not need to be saved. The following list summarizes the interrupt procedure: MCU - The interrupt is detected. - The C and Z flags are replaced by the interrupt flags (or by the NMI flags). - The PC contents are stored in the first level of the stack. - The normal interrupt lines are inhibited (NMI still active). - The first internal latch is cleared. - The associated interrupt vector is loaded in the PC. WARNING: In some circumstances, when a maskable interrupt occurs while the ST6 core is in NORMAL mode and especially during the execution of an "ldi IOR, 00h" instruction (disabling all maskable interrupts): if the interrupt arrives during the first 3 cycles of the "ldi" instruction (which is a 4-cycle instruction) the core will switch to interrupt mode BUT the flags CN and ZN will NOT switch to the interrupt pair CI and ZI. User - User selected registers are saved within the interrupt service routine (normally on a software stack). - The source of the interrupt is found by polling the interrupt flags (if more than one source is associated with the same vector). - The interrupt is serviced. - Return from interrupt (RETI)
MCU - Automatically the MCU switches back to the normal flag set (or the interrupt flag set) and pops the previous PC value from the stack. The interrupt routine usually begins by the identifying the device which generated the interrupt request (by polling). The user should save the registers which are used within the interrupt routine in a software stack. After the RETI instruction is executed, the MCU returns to the main routine.
Figure 16. Interrupt Processing Flow Chart
INSTRUCTION
FETCH INSTRUCTION
EXECUTE INSTRUCTION
WAS THE INSTRUCTION A RETI ? YES YES
NO
LOAD PC FROM INTERRUPT VECTOR (FFC/FFD)
?
NO CLEAR INTERRUPT MASK
IS THE CORE ALREADY IN NORMAL MODE?
SET INTERRUPT MASK
PUSH THE PC INTO THE STACK
SELECT PROGRAM FLAGS
SELECT INTERNAL MODE FLAG
"POP" THE STACKED PC
NO
?
YES
CHECK IF THERE IS AN INTERRUPT REQUEST AND INTERRUPT MASK
VA000014
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IINTERRUPTS (Cont'd) 3.4.3 Interrupt Option Register (IOR) The Interrupt Option Register (IOR) is used to enable/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed by single-bit operations. Address: 0C8h -- Write Only Reset status: 00h
7 LES ESB GEN 0 -
Bit 5 = ESB: Edge Selection bit. The bit ESB selects the polarity of the interrupt source #2. Bit 4 = GEN: Global Enable Interrupt. When this bit is set to one, all interrupts are enabled. When this bit is cleared to zero all the interrupts (excluding NMI) are disabled. When the GEN bit is low, the NMI interrupt is active but cannot cause a wake up from STOP/WAIT modes. This register is cleared on reset. 3.4.4 Interrupt Sources Interrupt sources available on the ST62E62B/T62B are summarized in the Table 10 with associated mask bit to enable/disable the interrupt request.
Bit 7, Bits 3-0 = Unused. Bit 6 = LES: Level/Edge Selection bit. When this bit is set to one, the interrupt source #1 is level sensitive. When cleared to zero the edge sensitive mode for interrupt request is selected. Table 10. Interrupt Requests and Mask Bits
Peripheral GENERAL TIMER A/D CONVERTER AR TIMER Port PAn Port PBn Port PCn Register IOR TSCR1 ADCR ARMC ORPA-DRPA ORPB-DRPB ORPC-DRPC Address Register C8h D4h D1h D5h C0h-C4h C1h-C5h C2h-C6h
Mask bit GEN ETI EAI OVIE CPIE EIE ORPAn-DRPAn ORPBn-DRPBn ORPCn-DRPCn
Masked Interrupt Source
Interrupt vector Vector 4 Vector 4 Vector 3 Vector 1 Vector 1 Vector 2
All Interrupts, excluding NMI
TMZ: TIMER Overflow EOC: End of Conversion OVF: AR TIMER Overflow CPF: Successful compare EF: Active edge on ARTIMin PAn pin PBn pin PCn pin
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INTERRUPTS (Cont'd) Figure 17. Interrupt Block Diagram
FROM REGISTER PORT A,B,C SINGLE BIT ENABLE PBE
V DD
PORT A PORT B Bits PBE
FF CLK Q CLR
0 I Start MUX 1 1 RESTART FROM STOP/WAIT INT #1 (FF6,7)
IOR REG. C8H, bit 6
PORT C Bits
PBE
FF CLK Q CLR IOR REG. C8H, bit 5 I Start 2
INT #2 (FF4,5)
OVF OVIE CPF AR TIMER CPIE EF EIE TIMER1 TMZ VDD ETI ADC EOC EAI NMI FF CLK Q CLR I0Start
INT #3 (FF2,3)
INT #4 (FF0,1)
NMI (FFC,D)
Bit GEN (IOR Register) VA0426P
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3.5 POWER SAVING MODES The WAIT and STOP modes have been implemented in the ST62xx family of MCUs in order to reduce the product's electrical consumption during idle periods. These two power saving modes are described in the following paragraphs. 3.5.1 WAIT Mode The MCU goes into WAIT mode as soon as the WAIT instruction is executed. The microcontroller can be considered as being in a "software frozen" state where the core stops processing the program instructions, the RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage. In this mode the peripherals are still active. WAIT mode can be used when the user wants to reduce the MCU power consumption during idle periods, while not losing track of time or the capability of monitoring external events. The active oscillator is not stopped in order to provide a clock signal to the peripherals. Timer counting may be enabled as well as the Timer interrupt, before entering the WAIT mode: this allows the WAIT mode to be exited when a Timer interrupt occurs. The same applies to other peripherals which use the clock signal. If the WAIT mode is exited due to a Reset (either by activating the external pin or generated by the Watchdog), the MCU enters a normal reset procedure. If an interrupt is generated during WAIT mode, the MCU's behaviour depends on the state of the processor core prior to the WAIT instruction, but also on the kind of interrupt request which is generated. This is described in the following paragraphs. The processor core does not generate a delay following the occurrence of the interrupt, because the oscillator clock is still available and no stabilisation period is necessary. 3.5.2 STOP Mode If the Watchdog is disabled, STOP mode is available. When in STOP mode, the MCU is placed in the lowest power consumption mode. In this operating mode, the microcontroller can be considered as being "frozen", no instruction is executed, the oscillator is stopped, the RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage, and the ST62xx core waits for the occurrence of an external interrupt request or a Reset to exit the STOP state. If the STOP state is exited due to a Reset (by activating the external pin) the MCU will enter a normal reset procedure. Behaviour in response to interrupts depends on the state of the processor core prior to issuing the STOP instruction, and also on the kind of interrupt request that is generated. This case will be described in the following paragraphs. The processor core generates a delay after occurrence of the interrupt request, in order to wait for complete stabilisation of the oscillator, before executing the first instruction.
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POWER SAVING MODE (Cont'd) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an interrupt occurs (not a Reset). It should be noted that the restart sequence depends on the original state of the MCU (normal, interrupt or non-maskable interrupt mode) prior to entering WAIT or STOP mode, as well as on the interrupt type. Interrupts do not affect the oscillator selection. 3.5.3.1 Normal Mode If the MCU was in the main routine when the WAIT or STOP instruction was executed, exit from Stop or Wait mode will occur as soon as an interrupt occurs; the related interrupt routine is executed and, on completion, the instruction which follows the STOP or WAIT instruction is then executed, providing no other interrupts are pending. 3.5.3.2 Non Maskable Interrupt Mode If the STOP or WAIT instruction has been executed during execution of the non-maskable interrupt routine, the MCU exits from the Stop or Wait mode as soon as an interrupt occurs: the instruction which follows the STOP or WAIT instruction is executed, and the MCU remains in non-maskable interrupt mode, even if another interrupt has been generated. 3.5.3.3 Normal Interrupt Mode If the MCU was in interrupt mode before the STOP or WAIT instruction was executed, it exits from STOP or WAIT mode as soon as an interrupt occurs. Nevertheless, two cases must be considered: - If the interrupt is a normal one, the interrupt routine in which the WAIT or STOP mode was en-
tered will be completed, starting with the execution of the instruction which follows the STOP or the WAIT instruction, and the MCU is still in the interrupt mode. At the end of this routine pending interrupts will be serviced in accordance with their priority. - In the event of a non-maskable interrupt, the non-maskable interrupt service routine is processed first, then the routine in which the WAIT or STOP mode was entered will be completed by executing the instruction following the STOP or WAIT instruction. The MCU remains in normal interrupt mode. Notes:
To achieve the lowest power consumption during RUN or WAIT modes, the user program must take care of: - configuring unused I/Os as inputs without pull-up (these should be externally tied to well defined logic levels); - placing all peripherals in their power down modes before entering STOP mode;
When the hardware activated Watchdog is selected, or when the software Watchdog is enabled, the STOP instruction is disabled and a WAIT instruction will be executed in its place. If all interrupt sources are disabled (GEN low), the MCU can only be restarted by a Reset. Although setting GEN low does not mask the NMI as an interrupt, it will stop it generating a wake-up signal. The WAIT and STOP instructions are not executed if an enabled interrupt request is pending.
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4 ON-CHIP PERIPHERALS
4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: - Input without pull-up or interrupt - Input with pull-up and interrupt - Input with pull-up, but without interrupt - Analog input - Push-pull output - Open drain output The lines are organised as bytewise Ports. Each port is associated with 3 registers in Data space. Each bit of these registers is associated with a particular line (for instance, bits 0 of Port A Data, Direction and Option registers are associated with the PA0 line of Port A). The DATA registers (DRx), are used to read the voltage level values of the lines which have been configured as inputs, or to write the logic value of the signal to be output on the lines configured as outputs. The port data registers can be read to get the effective logic levels of the pins, but they can Figure 18. I/O Port Block Diagram
SIN CONTROLS RESET VDD
be also written by user software, in conjunction with the related option registers, to select the different input mode options. Single-bit operations on I/O registers are possible but care is necessary because reading in input mode is done from I/O pins while writing will directly affect the Port data register causing an undesired change of the input configuration. The Data Direction registers (DDRx) allow the data direction (input or output) of each pin to be set. The Option registers (ORx) are used to select the different port options available both in input and in output mode. All I/O registers can be read or written to just as any other RAM location in Data space, so no extra RAM cells are needed for port data storage and manipulation. During MCU initialization, all I/O registers are cleared and the input mode with pullups and no interrupt generation is selected for all the pins, thus avoiding pin conflicts.
DATA DIRECTION REGISTER
VDD
INPUT/OUTPUT DATA REGISTER SHIFT REGISTER OPTION REGISTER
SOUT TO INTERRUPT TO ADC
VA00413
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I/O PORTS (Cont'd) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option registers (OR). Table 11 I/O Port Option Selection illustrates the various port configurations which can be selected by user software. 4.1.1.1 Input Options Pull-up, High Impedance Option. All input lines can be individually programmed with or without an internal pull-up by programming the OR and DR registers accordingly. If the pull-up option is not selected, the input pin will be in the high-impedance state. Table 11. I/O Port Option Selection
DDR 0 0 0 0 1 1 OR 0 0 1 1 0 1 DR 0 1 0 1 X X Mode Input Input Input Input Output Output
4.1.1.2 Interrupt Options All input lines can be individually connected by software to the interrupt system by programming the OR and DR registers accordingly. The interrupt trigger modes (falling edge, rising edge and low level) can be configured by software as described in the Interrupt Chapter for each port. 4.1.1.3 Analog Input Options Some pins can be configured as analog inputs by programming the OR and DR registers accordingly. These analog inputs are connected to the onchip 8-bit Analog to Digital Converter. ONLY ONE pin should be programmed as an analog input at any time, since by selecting more than one input simultaneously their pins will be effectively shorted.
Option With pull-up, no interrupt No pull-up, no interrupt With pull-up and with interrupt Analog input (when available) Open-drain output (20mA sink when available) Push-pull output (20mA sink when available)
Note: X = Don't care
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I/O PORTS (Cont'd) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recommended safe transitions are illustrated in Figure 19.. All other transitions are potentially risky and should be avoided when changing the I/O operating mode, as it is most likely that undesirable sideeffects will be experienced, such as spurious interrupt generation or two pins shorted together by the analog multiplexer. Single bit instructions (SET, RES, INC and DEC) should be used with great caution on Ports Data registers, since these instructions make an implicit read and write back of the entire register. In port input mode, however, the data register reads from the input pins directly, and not from the data register latches. Since data register information in input mode is used to set the characteristics of the input pin (interrupt, pull-up, analog input), these may be unintentionally reprogrammed depending on the state of the input pins. As a general rule, it is better to limit the use of single bit instructions on data registers to when the whole (8-bit) port is in output mode. In the case of inputs or of mixed inputs and
outputs, it is advisable to keep a copy of the data register in RAM. Single bit instructions may then be used on the RAM copy, after which the whole copy register can be written to the port data register: SET bit, datacopy LD a, datacopy LD DRA, a Warning: Care must also be taken to not use instructions that act on a whole port register (INC, DEC, or read operations) when all 8 bits are not available on the device. Unavailable bits must be masked by software (AND instruction). The WAIT and STOP instructions allow the ST62xx to be used in situations where low power consumption is needed. The lowest power consumption is achieved by configuring I/Os in input mode with well-defined logic levels. The user must take care not to switch outputs with heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to the conversion.
Figure 19. Diagram showing Safe I/O State Transitions Interrupt pull-up Input pull-up (Reset state) Output Open Drain Output Push-pull Input Analog Input
010*
011
000
001
100
101
Output Open Drain Output Push-pull
110
111
Note *. xxx = DDR, OR, DR Bits respectively
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I/O PORTS (Cont'd) Table 12. I/O Port Option Selections
MODE Input Reset state( AVAILABLE ON(1) SCHEMATIC
PA4-PA5 PB0, PB6-PB7 PC2-PC3 Data in
Reset state if PULL-UP PB2-PB3, option disabled Input Reset state PA4-PA5 PB0,,PB6-PB7 PC2-PC3 Reset state if PULL-UP option enabled PB2-PB3
Interrupt
Data in Interrupt
Input with pull up with interrupt
PA4-PA5 PB0, PB2-PB3,PB6-PB7 PC2-PC3 Data in Interrupt
Analog Input
PA4-PA5 PC2-PC3 ADC
Open drain output 5mA Open drain output 20mA
PA4-PA5 PC2-PC3 Data out PB0, PB2-PB3,PB6-PB7
Push-pull output 5mA Push-pull output 20mA
PA4-PA5 PC2-PC3 Data out PB0, PB2-PB3,PB6-PB7
Note 1. Provided the correct configuration has been selected.
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I/O PORTS (Cont'd) 4.1.3 ARTimer alternate functions When bit PWMOE of register ARMC is low, pin ARTIMout/PB7 is configured as any standard pin of port B through the port registers. When PWMOE is high, ARTMout/PB7 is the PWM output, independently of the port registers configuration.
ARTIMin/PB6 is connected to the AR Timer input. It is configured through the port registers as any standard pin of port B. To use ARTIMin/PB6 as AR Timer input, it must be configured as input through DDRB.
Figure 20. Peripheral Interface Configuration of AR Timer
PID ARTIMin ARTIMin DR
AR TIMER
PID OR PWMOE ARTIMout MUX 1 0 ARTIMout DR VR01661G
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4.2 TIMER The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit programmable prescaler, giving a maximum count of 215. Figure 21. shows the Timer Block Diagram. The content of the 8-bit counter can be read/written in the Timer/Counter register, TCR, which can be addressed in Data space as a RAM location at address 0D3h. The state of the 7-bit prescaler can be read in the PSC register at address 0D2h. The control logic device is managed in the TSCR register as described in the following paragraphs. The 8-bit counter is decrement by the output (rising edge) coming from the 7-bit prescaler and can be loaded and read under program control. When it decrements to zero then the TMZ (Timer Zero)bit in the TSCR is set. If the ETI (Enable Timer Interrupt) bit in the TSCR is also set, an interrupt request is generated. The Timer interrupt can be used to exit the MCU from WAIT mode. The prescaler input is the internal frequency (fINT) divided by 12. The prescaler decrements on the rising edge. Depending on the division factor programmed by PS2, PS1 and PS0 bits in the TSCR (see Table 13.), the clock input of the timer/counter register is multiplexed to different sources. For division factor 1, the clock input of the prescaler is also that of timer/counter; for factor 2, bit 0 of the prescaler register is connected to the clock input of TCR. This bit changes its state at half the frequency of the prescaler input clock. For factor 4, bit 1 of the PSC is connected to the clock input of TCR, and so forth. The prescaler initialize bit, PSI, in the TSCR register must be set to allow the prescaler (and hence the counter) to start. If it is cleared, all the prescaler bits are set and the counter is inhibited from counting. The prescaler can be loaded with any value between 0 and 7Fh, if bit PSI is set. The prescaler tap is selected by means of the PS2/PS1/PS0 bits in the control register. Figure 22. illustrates the Timer's working principle.
Figure 21. Timer Block Diagram
.
DATA BUS 8 6 5 4 3 2 1 0 8 8-BIT SELECT 1 OF 7 b7 b6 b5 8 b4 b3 b2 b1 b0
PSC
STATUS/CONTROL REGISTER
TMZ ETI D5 D4 PSI PS2 PS1 PS0
fINT
12
/
3
INTERRUPT LINE
VR02070A
.
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TIMER (Cont'd) 4.2.1 Timer Operation The Timer prescaler is clocked by the prescaler clock input (fINT / 12). The user can select the desired prescaler division ratio through the PS2, PS1, PS0 bits. When the TCR count reaches 0, it sets the TMZ bit in the TSCR. The TMZ bit can be tested under program control to perform a timer function whenever it goes high. 4.2.2 Timer Interrupt When the counter register decrements to zero with the ETI (Enable Timer Interrupt) bit set to one, an interrupt request associated with Interrupt Vector #3 is generated. When the counter decrements Figure 22. Timer Working Principle
to zero, the TMZ bit in the TSCR register is set to one. 4.2.3 Application Notes TMZ is set when the counter reaches zero; however, it may also be set by writing 00h in the TCR register or by setting bit 7 of the TSCR register. The TMZ bit must be cleared by user software when servicing the timer interrupt to avoid undesired interrupts when leaving the interrupt service routine. After reset, the 8-bit counter register is loaded with 0FFh, while the 7-bit prescaler is loaded with 07Fh, and the TSCR register is cleared. This means that the Timer is stopped (PSI="0") and the timer interrupt is disabled.
7-BIT PRESCALER CLOCK BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6
0
1
2
3 4 8-1 MULTIPLEXER
5
6
7
PS0 PS1 PS2
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
8-BIT COUNTER
VA00186
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TIMER (Cont'd) A write to the TCR register will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the TMZ bit is not set until the 8-bit counter reaches 00h again. The values of the TCR and the PSC registers can be read accurately at any time. 4.2.4 Timer Registers Timer Status Control Register (TSCR) Address: 0D4h -- Read/Write
7 TMZ ETI D5 D4 PSI PS2 PS1 0 PS0
long as PSI="0" both counter and prescaler are not running. Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Select. These bits select the division ratio of the prescaler register. Table 13. Prescaler Division Factors
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 Divided by 1 2 4 8 16 32 64 128
Bit 7 = TMZ: Timer Zero bit A low-to-high transition indicates that the timer count register has decrement to zero. This bit must be cleared by user software before starting a new count. Bit 6 = ETI: Enable Timer Interrup When set, enables the timer interrupt request (vector #3). If ETI=0 the timer interrupt is disabled. If ETI=1 and TMZ=1 an interrupt request is generated. Bit 5 = D5: Reserved Must be set to "1". Bit 4 = D4 Do not care. Bit 3 = PSI: Prescaler Initialize Bit Used to initialize the prescaler and inhibit its counting. When PSI="0" the prescaler is set to 7Fh and the counter is inhibited. When PSI="1" the prescaler is enabled to count downwards. As
Timer Counter Register (TCR) Address: 0D3h -- Read/Write
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7-0 = D7-D0: Counter Bits. Prescaler Register PSC Address: 0D2h -- Read/Write
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = D7: Always read as "0". Bit 6-0 = D6-D0: Prescaler Bits.
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4.3 AUTO-RELOAD TIMER The Auto-Reload Timer (AR Timer) on-chip peripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to be selected as fINT, fINT/3 or an external clock source. A Mode Control Register, ARMC, two Status Control Registers, ARSC0 and ARSC1, an output pin, ARTIMout, and an input pin, ARTIMin, allow the Auto-Reload Timer to be used in 4 modes: - Auto-reload (PWM generation), - Output compare and reload on external event (PLL), - Input capture and output compare for time measurement. - Input capture and output compare for period measurement. The AR Timer can be used to wake the MCU from WAIT mode either with an internal or with an external clock. It also can be used to wake the MCU from STOP mode, if used with an external clock signal connected to the ARTIMin pin. A Load register allows the program to read and write the counter on the fly. 4.3.1 AR Timer Description The AR COUNTER is an 8-bit up-counter incremented on the input clock's rising edge. The counter is loaded from the ReLoad/Capture Register, ARRC, for auto-reload or capture operations, as well as for initialization. Direct access to the AR counter is not possible; however, by reading or writing the ARLR load register, it is possible to read or write the counter's contents on the fly. The AR Timer's input clock can be either the internal clock (from the Oscillator Divider), the internal clock divided by 3, or the clock signal connected to the ARTIMin pin. Selection between these clock sources is effected by suitably programming bits CC0-CC1 of the ARSC1 register. The output of the AR Multiplexer feeds the 7-bit programmable AR Prescaler, ARPSC, which selects one of the 8 available taps of the prescaler, as defined by PSC0-PSC2 in the AR Mode Control Register. Thus the division factor of the prescaler can be set to 2n (where n = 0, 1,..7). The clock input to the AR counter is enabled by the TEN (Timer Enable) bit in the ARMC register. When TEN is reset, the AR counter is stopped and the prescaler and counter contents are frozen. When TEN is set, the AR counter runs at the rate of the selected clock source. The counter is cleared on system reset. The AR counter may also be initialized by writing to the ARLR load register, which also causes an immediate copy of the value to be placed in the AR counter, regardless of whether the counter is running or not. Initialization of the counter, by either method, will also clear the ARPSC register, whereupon counting will start from a known value. 4.3.2 Timer Operating Modes Four different operating modes are available for the AR Timer: Auto-reload Mode with PWM Generation. This mode allows a Pulse Width Modulated signal to be generated on the ARTIMout pin with minimum Core processing overhead. The free running 8-bit counter is fed by the prescaler's output, and is incremented on every rising edge of the clock signal. When a counter overflow occurs, the counter is automatically reloaded with the contents of the Reload/Capture Register, ARCC, and ARTIMout is set. When the counter reaches the value contained in the compare register (ARCP), ARTIMout is reset. On overflow, the OVF flag of the ARSC0 register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OVIE, in the Mode Control Register (ARMC), is set. The OVF flag must be reset by the user software. When the counter reaches the compare value, the CPF flag of the ARSC0 register is set and a compare interrupt request is generated, if the Compare Interrupt enable bit, CPIE, in the Mode Control Register (ARMC), is set. The interrupt service routine may then adjust the PWM period by loading a new value into ARCP. The CPF flag must be reset by user software. The PWM signal is generated on the ARTIMout pin (refer to the Block Diagram). The frequency of this signal is controlled by the prescaler setting and by the auto-reload value present in the Reload/Capture register, ARRC. The duty cycle of the PWM signal is controlled by the Compare Register, ARCP.
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AUTO-RELOAD TIMER (Cont'd) Figure 23. . AR Timer Block Diagram
DATA BUS DDRB7
8 DRB7 AR COMPARE REGISTER
8 PB7/ ARTIMout CPF COMPARE R S 8 PWMOE OVF 7-Bit AR PRESCALER 8-Bit AR COUNTER LOAD OVF OVIE TCLD
f INT f INT /3
M U X
CC0-CC1
PS0-PS2
EIE EF 8 CPF CPIE AR TIMER INTERRUPT
8
8
PB6/ ARTIMin SL0-SL1 EF SYNCHRO AR RELOAD/CAPTURE REGISTER AR LOAD REGISTER
8 DATA BUS
8
VR01660A
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AUTO-RELOAD TIMER (Cont'd) It should be noted that the reload values will also affect the value and the resolution of the duty cycle of PWM output signal. To obtain a signal on ARTIMout, the contents of the ARCP register must be greater than the contents of the ARRC register. The maximum available resolution for the ARTIMout duty cycle is: Resolution = 1/[255-(ARRC)] Where ARRC is the content of the Reload/Capture register. The compare value loaded in the Compare Register, ARCP, must be in the range from (ARRC) to 255. Figure 24. . Auto-reload Timer PWM Function
COUNTER 255 COMPARE VALUE
The ARTC counter is initialized by writing to the ARRC register and by then setting the TCLD (Timer Load) and the TEN (Timer Clock Enable) bits in the Mode Control register, ARMC. Enabling and selection of the clock source is controlled by the CC0, CC1, SL0 and SL1 bits in the Status Control Register, ARSC1. The prescaler division ratio is selected by the PS0, PS1 and PS2 bits in the ARSC1 register. In Auto-reload Mode, any of the three available clock sources can be selected: Internal Clock, Internal Clock divided by 3 or the clock signal present on the ARTIMin pin.
RELOAD REGISTER 000
t
PWM OUTPUT
t
VR001852
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AUTO-RELOAD TIMER (Cont'd) Capture Mode with PWM Generation. In this mode, the AR counter operates as a free running 8-bit counter fed by the prescaler output. The counter is incremented on every clock rising edge. An 8-bit capture operation from the counter to the ARRC register is performed on every active edge on the ARTIMin pin, when enabled by Edge Control bits SL0, SL1 in the ARSC1 register. At the same time, the External Flag, EF, in the ARSC0 register is set and an external interrupt request is generated if the External Interrupt Enable bit, EIE, in the ARMC register, is set. The EF flag must be reset by user software. Each ARTC overflow sets ARTIMout, while a match between the counter and ARCP (Compare Register) resets ARTIMout and sets the compare flag, CPF. A compare interrupt request is generated if the related compare interrupt enable bit, CPIE, is set. A PWM signal is generated on ARTIMout. The CPF flag must be reset by user software. The frequency of the generated signal is determined by the prescaler setting. The duty cycle is determined by the ARCP register. Initialization and reading of the counter are identical to the auto-reload mode (see previous description). Enabling and selection of clock sources is controlled by the CC0 and CC1 bits in the AR Status Control Register, ARSC1. The prescaler division ratio is selected by programming the PS0, PS1 and PS2 bits in the ARSC1 Register. In Capture mode, the allowed clock sources are the internal clock and the internal clock divided by 3; the external ARTIMin input pin should not be used as a clock source. Capture Mode with Reset of counter and prescaler, and PWM Generation. This mode is identical to the previous one, with the difference that a capture condition also resets the counter and the prescaler, thus allowing easy measurement of the time between two captures (for input period measurement on the ARTIMin pin). Load on External Input. The counter operates as a free running 8-bit counter fed by the prescaler. the count is incremented on every clock rising edge.
Each counter overflow sets the ARTIMout pin. A match between the counter and ARCP (Compare Register) resets the ARTIMout pin and sets the compare flag, CPF. A compare interrupt request is generated if the related compare interrupt enable bit, CPIE, is set. A PWM signal is generated on ARTIMout. The CPF flag must be reset by user software. Initialization of the counter is as described in the previous paragraph. In addition, if the external ARTIMin input is enabled, an active edge on the input pin will copy the contents of the ARRC register into the counter, whether the counter is running or not. Notes: The allowed AR Timer clock sources are the following:
AR Timer Mode Auto-reload mode Capture mode Capture/Reset mode External Load mode Clock Sources fINT, fINT/3, ARTIMin fINT, fINT/3 fINT, fINT/3 fINT, fINT/3
The clock frequency should not be modified while the counter is counting, since the counter may be set to an unpredictable value. For instance, the multiplexer setting should not be modified while the counter is counting. Loading of the counter by any means (by auto-reload, through ARLR, ARRC or by the Core) resets the prescaler at the same time. Care should be taken when both the Capture interrupt and the Overflow interrupt are used. Capture and overflow are asynchronous. If the capture occurs when the Overflow Interrupt Flag, OVF, is high (between counter overflow and the flag being reset by software, in the interrupt routine), the External Interrupt Flag, EF, may be cleared simultaneusly without the interrupt being taken into account. The solution consists in resetting the OVF flag by writing 06h in the ARSC0 register. The value of EF is not affected by this operation. If an interrupt has occured, it will be processed when the MCU exits from the interrupt routine (the second interrupt is latched).
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AUTO-RELOAD TIMER (Cont'd) 4.3.3 AR Timer Registers AR Mode Control Register (ARMC) Address: D5h -- Read/Write Reset status: 00h
7 TCLD TEN PWMOE EIE CPIE 0 OVIE ARMC1 ARMC0
the ARSC0 register is also set, an interrupt request is generated. Bit 1-0 = ARMC1-ARMC0: Mode Control Bits 1-0. These are the operating mode control bits. The following bit combinations will select the various operating modes:
ARMC1 0 0 1 1 ARMC0 0 1 0 1 Operating Mode Auto-reload Mode Capture Mode Capture Mode with Reset of ARTC and ARPSC Load on External Edge Mode
The AR Mode Control Register ARMC is used to program the different operating modes of the AR Timer, to enable the clock and to initialize the counter. It can be read and written to by the Core and it is cleared on system reset (the AR Timer is disabled). Bit 7 = TLCD: Timer Load Bit. This bit, when set, will cause the contents of ARRC register to be loaded into the counter and the contents of the prescaler register, ARPSC, are cleared in order to initialize the timer before starting to count. This bit is write-only and any attempt to read it will yield a logical zero. Bit 6 = TEN: Timer Clock Enable. This bit, when set, allows the timer to count. When cleared, it will stop the timer and freeze ARPSC and ARTSC. Bit 5 = PWMOE: PWM Output Enable. This bit, when set, enables the PWM output on the ARTIMout pin. When reset, the PWM output is disabled. Bit 4 = EIE: External Interrupt Enable. This bit, when set, enables the external interrupt request. When reset, the external interrupt request is masked. If EIE is set and the related flag, EF, in the ARSC0 register is also set, an interrupt request is generated. Bit 3 = CPIE: Compare Interrupt Enable. This bit, when set, enables the compare interrupt request. If CPIE is reset, the compare interrupt request is masked. If CPIE is set and the related flag, CPF, in the ARSC0 register is also set, an interrupt request is generated. Bit 2 = OVIE: Overflow Interrupt. This bit, when set, enables the overflow interrupt request. If OVIE is reset, the compare interrupt request is masked. If OVIE is set and the related flag, OVF in
AR Timer Status/Control Registers ARSC0 & ARSC1. These registers contain the AR Timer status information bits and also allow the programming of clock sources, active edge and prescaler multiplexer setting. ARSC0 register bits 0,1 and 2 contain the interrupt flags of the AR Timer. These bits are read normally. Each one may be reset by software. Writing a one does not affect the bit value. AR Status Control Register 0 (ARSC0) Address: D6h -- Read/Clear
7 D7 D6 D5 D4 D3 EF CPF 0 OVF
Bits 7-3 = D7-D3: Unused Bit 2 = EF: External Interrupt Flag. This bit is set by any active edge on the external ARTIMin input pin. The flag is cleared by writing a zero to the EF bit. Bit 1 = CPF: Compare Interrupt Flag. This bit is set if the contents of the counter and the ARCP register are equal. The flag is cleared by writing a zero to the CPF bit. Bit 0 = OVF: Overflow Interrupt Flag. This bit is set by a transition of the counter from FFh to 00h (overflow). The flag is cleared by writing a zero to the OVF bit.
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AUTO-RELOAD TIMER (Cont'd) AR Status Control Register 1(ARSC1) Address: D7h -- Read/Write
7 PS2 PS1 PS0 D4 SL1 SL0 CC1 0 CC0
AR Load Register ARLR. The ARLR load register is used to read or write the ARTC counter register "on the fly" (while it is counting). The ARLR register is not affected by system reset. AR Load Register (ARLR) Address: DBh -- Read/Write
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bist 7-5 = PS2-PS0: Prescaler Division Selection Bits 2-0. These bits determine the Prescaler division ratio. The prescaler itself is not affected by these bits. The prescaler division ratio is listed in the following table: Table 14. . Prescaler Division Ratio Selection
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 ARPSC Division Ratio 1 2 4 8 16 32 64 128
Bit 7-0 = D7-D0: Load Register Data Bits. These are the load register data bits. AR Reload/Capture Register. The ARRC reload/capture register is used to hold the auto-reload value which is automatically loaded into the counter when overflow occurs. AR Reload/Capture (ARRC) Address: D9h -- Read/Write
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 4 = D4: Reserved. Must be kept reset. Bit 3-2 = SL1-SL0: Timer Input Edge Control Bits 10. These bits control the edge function of the Timer input pin for external synchronization. If bit SL0 is reset, edge detection is disabled; if set edge detection is enabled. If bit SL1 is reset, the AR Timer input pin is rising edge sensitive; if set, it is falling edge sensitive.
SL1 X 0 1 SL0 0 1 1 Edge Detection Disabled Rising Edge Falling Edge
Bit 7-0 = D7-D0: Reload/Capture Data Bits. These are the Reload/Capture register data bits. AR Compare Register. The CP compare register is used to hold the compare value for the compare function. AR Compare Register (ARCP) Address: DAh -- Read/Write
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 1-0 = CC1-CC0: Clock Source Select Bit 1-0. These bits select the clock source for the AR Timer through the AR Multiplexer. The programming of the clock sources is explained in the following Table 15 . Clock Source Selection.: Table 15. . Clock Source Selection.
CC1 0 0 1 1 CC0 0 1 0 1 Clock Source Fint Fint Divided by 3 ARTIMin Input Clock Reserved
Bit 7-0 = D7-D0: Compare Data Bits. These are the Compare register data bits.
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4.4 A/D CONVERTER (ADC) The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device dependent), offering 8-bit resolution with a typical conversion time of 70us (at an oscillator clock frequency of 8MHz). The ADC converts the input voltage by a process of successive approximations, using a clock frequency derived from the oscillator with a division factor of twelve. With an oscillator clock frequency less than 1.2MHz, conversion accuracy is decreased. Selection of the input pin is done by configuring the related I/O line as an analog input via the Option and Data registers (refer to I/O ports description for additional information). Only one I/O line must be configured as an analog input at any time. The user must avoid any situation in which more than one I/O pin is selected as an analog input simultaneously, to avoid device malfunction. The ADC uses two registers in the data space: the ADC data conversion register, ADR, which stores the conversion result, and the ADC control register, ADCR, used to program the ADC functions. A conversion is started by writing a "1" to the Start bit (STA) in the ADC control register. This automatically clears (resets to "0") the End Of Conversion Bit (EOC). When a conversion is complete, the EOC bit is automatically set to "1", in order to flag that conversion is complete and that the data in the ADC data conversion register is valid. Each conversion has to be separately initiated by writing to the STA bit. The STA bit is continuously scanned so that, if the user sets it to "1" while a previous conversion is in progress, a new conversion is started before completing the previous one. The start bit (STA) is a write only bit, any attempt to read it will show a logical "0". The A/D converter features a maskable interrupt associated with the end of conversion. This interrupt is associated with interrupt vector #4 and occurs when the EOC bit is set (i.e. when a conversion is completed). The interrupt is masked using the EAI (interrupt mask) bit in the control register. The power consumption of the device can be reduced by turning off the ADC peripheral. This is done by setting the PDS bit in the ADC control register to "0". If PDS="1", the A/D is powered and enabled for conversion. This bit must be set at least one instruction before the beginning of the conversion to allow stabilisation of the A/D converter. This action is also needed before entering WAIT mode, since the A/D comparator is not automatically disabled in WAIT mode. During Reset, any conversion in progress is stopped, the control register is reset to 40h and the ADC interrupt is masked (EAI=0). Figure 25. ADC Block Diagram
Ain
CONVERTER
INTERRUPT CLOCK RESET AVSS AVDD
CONTROL REGISTER 8 CORE CONTROL SIGNALS
RESULT REGISTER 8 CORE
VA00418
4.4.1 Application Notes The A/D converter does not feature a sample and hold circuit. The analog voltage to be measured should therefore be stable during the entire conversion cycle. Voltage variation should not exceed 1/2 LSB for the optimum conversion accuracy. A low pass filter may be used at the analog input pins to reduce input voltage variation during conversion. When selected as an analog channel, the input pin is internally connected to a capacitor Cad of typically 12pF. For maximum accuracy, this capacitor must be fully charged at the beginning of conversion. In the worst case, conversion starts one instruction (6.5 s) after the channel has been selected. In worst case conditions, the impedance, ASI, of the analog voltage source is calculated using the following formula: 6.5s = 9 x Cad x ASI (capacitor charged to over 99.9%), i.e. 30 k including a 50% guardband. ASI can be higher if Cad has been charged for a longer period by adding instructions before the start of conversion (adding more than 26 CPU cycles is pointless).
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A/D CONVERTER (Cont'd) Since the ADC is on the same chip as the microprocessor, the user should not switch heavily loaded output signals during conversion, if high precision is required. Such switching will affect the supply voltages used as analog references. The accuracy of the conversion depends on the quality of the power supplies (VDD and VSS). The user must take special care to ensure a well regulated reference voltage is present on the VDD and VSS pins (power supply voltage variations must be less than 5V/ms). This implies, in particular, that a suitable decoupling capacitor is used at the VDD pin. The converter resolution is given by::
up the microcontroller could also be done using the Timer interrupt, but in this case the Timer will be working and the resulting noise could affect conversion accuracy. A/D Converter Control Register (ADCR) Address: 0D1h -- Read/Write
7 EAI EOC STA PDS D3 D2 D1 0 D0
V DD - V S S --------------------------256
The Input voltage (Ain) which is to be converted must be constant for 1s before conversion and remain constant during conversion. Conversion resolution can be improved if the power supply voltage (VDD) to the microcontroller is lowered. In order to optimise conversion resolution, the user can configure the microcontroller in WAIT mode, because this mode minimises noise disturbances and power supply variations due to output switching. Nevertheless, the WAIT instruction should be executed as soon as possible after the beginning of the conversion, because execution of the WAIT instruction may cause a small variation of the VDD voltage. The negative effect of this variation is minimized at the beginning of the conversion when the converter is less sensitive, rather than at the end of conversion, when the less significant bits are determined. The best configuration, from an accuracy standpoint, is WAIT mode with the Timer stopped. Indeed, only the ADC peripheral and the oscillator are then still working. The MCU must be woken up from WAIT mode by the ADC interrupt at the end of the conversion. It should be noted that waking
Bit 7 = EAI: Enable A/D Interrupt. If this bit is set to "1" the A/D interrupt is enabled, when EAI=0 the interrupt is disabled. Bit 6 = EOC: End of conversion. Read Only. This read only bit indicates when a conversion has been completed. This bit is automatically reset to "0" when the STA bit is written. If the user is using the interrupt option then this bit can be used as an interrupt pending bit. Data in the data conversion register are valid only when this bit is set to "1". Bit 5 = STA: Start of Conversion. Write Only. Writing a "1" to this bit will start a conversion on the selected channel and automatically reset to "0" the EOC bit. If the bit is set again when a conversion is in progress, the present conversion is stopped and a new one will take place. This bit is write only, any attempt to read it will show a logical zero. Bit 4 = PDS: Power Down Selection. This bit activates the A/D converter if set to "1". Writing a "0" to this bit will put the ADC in power down mode (idle mode). Bit 3-0 = D3-D0. Not used A/D Converter Data Register (ADR) Address: 0D0h -- Read only
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7-0 = D7-D0: 8 Bit A/D Conversion Result.
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5 SOFTWARE
5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 core has the ability to set or clear any register or RAM location bit of the Data space with a single instruction. Furthermore, the program may branch to a selected address depending on the status of any bit of the Data space. The carry bit is stored with the value of the bit when the SET or RES instruction is processed. 5.2 ADDRESSING MODES The ST6 core offers nine addressing modes, which are described in the following paragraphs. Three different address spaces are available: Program space, Data space, and Stack space. Program space contains the instructions which are to be executed, plus the data for immediate mode instructions. Data space contains the Accumulator, the X,Y,V and W registers, peripheral and Input/Output registers, the RAM locations and Data ROM locations (for storage of tables and constants). Stack space contains six 12-bit RAM cells used to stack the return addresses for subroutines and interrupts. Immediate. In the immediate addressing mode, the operand of the instruction follows the opcode location. As the operand is a ROM byte, the immediate addressing mode is used to access constants which do not change during program execution (e.g., a constant used to initialize a loop counter). Direct. In the direct addressing mode, the address of the byte which is processed by the instruction is stored in the location which follows the opcode. Direct addressing allows the user to directly address the 256 bytes in Data Space memory with a single two-byte instruction. Short Direct. The core can address the four RAM registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in the short-direct addressing mode. In this case, the instruction is only one byte and the selection of the location to be processed is contained in the opcode. Short direct addressing is a subset of the direct addressing mode. (Note that 80h and 81h are also indirect registers). Extended. In the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four less significant bits of the opcode with the byte following the opcode. The instructions (JP, CALL) which use the extended addressing mode are able to branch to any address of the 4K bytes Program space. An extended addressing mode instruction is twobyte long. Program Counter Relative. The relative addressing mode is only used in conditional branch instructions. The instruction is used to perform a test and, if the condition is true, a branch with a span of -15 to +16 locations around the address of the relative instruction. If the condition is not true, the instruction which follows the relative instruction is executed. The relative addressing mode instruction is one-byte long. The opcode is obtained in adding the three most significant bits which characterize the kind of the test, one bit which determines whether the branch is a forward (when it is 0) or backward (when it is 1) branch and the four less significant bits which give the span of the branch (0h to Fh) which must be added or subtracted to the address of the relative instruction to obtain the address of the branch. Bit Direct. In the bit direct addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode points to the address of the byte in which the specified bit must be set or cleared. Thus, any bit in the 256 locations of Data space memory can be set or cleared. Bit Test & Branch. The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit test and branch instruction is three-byte long. The bit identification and the tested condition are included in the opcode byte. The address of the byte to be tested follows immediately the opcode in the Program space. The third byte is the jump displacement, which is in the range of -127 to +128. This displacement can be determined using a label, which is converted by the assembler. Indirect. In the indirect addressing mode, the byte processed by the register-indirect instruction is at the address pointed by the content of one of the indirect registers, X or Y (80h,81h). The indirect register is selected by the bit 4 of the opcode. A register indirect instruction is one byte long. Inherent. In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. These instructions are one byte long.
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5.3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be divided into six different types: load/store, arithmetic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following paragraphs describe the different types. All the instructions belonging to a given type are presented in individual tables. Table 16. Load & Store Instructions
Instruction LD A, X LD A, Y LD A, V LD A, W LD X, A LD Y, A LD V, A LD W, A LD A, rr LD rr, A LD A, (X) LD A, (Y) LD (X), A LD (Y), A LDI A, #N LDI rr, #N Addressing Mode Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Indirect Indirect Immediate Immediate Bytes 1 1 1 1 1 1 1 1 2 2 1 1 1 1 2 3 Cycles 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Flags Z * C * * * * * * * * * * * * * * * *
Load & Store. These instructions use one, two or three bytes in relation with the addressing mode. One operand is the Accumulator for LOAD and the other operand is obtained from data memory using one of the addressing modes. For Load Immediate one operand can be any of the 256 data space bytes while the other is always immediate data.
Notes: X,Y. Indirect Register Pointers, V & W Short Direct Registers # . Immediate data (stored in ROM memory) rr. Data space register . Affected * . Not Affected
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INSTRUCTION SET (Cont'd) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instructions one operand is always the accumulator while the other can be either a data space memory conTable 17. Arithmetic & Logic Instructions
Instruction ADD A, (X) ADD A, (Y) ADD A, rr ADDI A, #N AND A, (X) AND A, (Y) AND A, rr ANDI A, #N CLR A CLR r COM A CP A, (X) CP A, (Y) CP A, rr CPI A, #N DEC X DEC Y DEC V DEC W DEC A DEC rr DEC (X) DEC (Y) INC X INC Y INC V INC W INC A INC rr INC (X) INC (Y) RLC A SLA A SUB A, (X) SUB A, (Y) SUB A, rr SUBI A, #N Addressing Mode Indirect Indirect Direct Immediate Indirect Indirect Direct Immediate Short Direct Direct Inherent Indirect Indirect Direct Immediate Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Inherent Inherent Indirect Indirect Direct Immediate Bytes 1 1 2 2 1 1 2 2 2 3 1 1 1 2 2 1 1 1 1 2 2 1 1 1 1 1 1 2 2 1 1 1 2 1 1 2 2 Cycles 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Flags Z * C * * * * * * * * * * * * * * * * *
tent or an immediate value in relation with the addressing mode. In CLR, DEC, INC instructions the operand can be any of the 256 data space addresses. In COM, RLC, SLA the operand is always the accumulator.
Notes: X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected # . Immediate data (stored in ROM memory)* . Not Affected rr. Data space register
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INSTRUCTION SET (Cont'd) Conditional Branch. The branch instructions achieve a branch in the program when the selected condition is met. Bit Manipulation Instructions. These instructions can handle any bit in data space memory. One group either sets or clears. The other group (see Conditional Branch) performs the bit test branch operations. Table 18. Conditional Branch Instructions
Instruction JRC e JRNC e JRZ e JRNZ e JRR b, rr, ee JRS b, rr, ee Branch If C=1 C=0 Z=1 Z=0 Bit = 0 Bit = 1 Bytes 1 1 1 1 3 3 Cycles 2 2 2 2 5 5 Flags Z * * * * * * C * * * *
Control Instructions. The control instructions control the MCU operations during program execution. Jump and Call. These two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space.
Notes: b. 3-bit address e. 5 bit signed displacement in the range -15 to +16 ee. 8 bit signed displacement in the range -126 to +129
rr. Data space register . Affected. The tested bit is shifted into carry. * . Not Affected
Table 19. Bit Manipulation Instructions
Instruction SET b,rr RES b,rr
Notes: b. 3-bit address; rr. Data space register;
Addressing Mode Bit Direct Bit Direct
Bytes 2 2
Cycles 4 4
* . Not Affected
Flags Z * * C * *
Table 20. Control Instructions
Instruction NOP RET RETI STOP (1) WAIT Addressing Mode Inherent Inherent Inherent Inherent Inherent Bytes 1 1 1 1 1 Cycles 2 2 2 2 2 Flags Z * * * * C * * * *
Notes: 1. This instruction is deactivatedand a WAIT is automatically executed instead of a STOP if the watchdog function is selected. . Affected *. Not Affected
Table 21. Jump & Call Instructions
Instruction CALL abc JP abc
Notes: abc. 12-bit address; * . Not Affected
Addressing Mode Extended Extended
Bytes 2 2
Cycles 4 4
Flags Z * * C * *
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Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW HI 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 0 0000 JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr RNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 1 0001 CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 0010 JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 3 0011 JRR b0,rr,ee bt JRS b0,rr,ee bt JRR b4,rr,ee bt JRS b4,rr,ee bt JRR b2,rr,ee bt JRS b2,rr,ee bt JRR b6,rr,ee bt JRS b6,rr,ee bt JRR b1,rr,ee bt JRS b1,rr,ee bt JRR b5,rr,ee bt JRS b5,rr,ee bt JRR b3,rr,ee bt JRS b3,rr,ee bt JRR b7,rr,ee bt JRS b7,rr,ee bt 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 pcr 1 pcr JRZ 4 a,w sd 1 pcr 1 JRZ # 1 LD 2 e prc pcr JRZ 4 w sd 1 2 e prc 1 JRC pcr 1 JRZ # 1 INC 2 e prc 2 JRC 4 pcr JRZ 4 a,v sd 1 2 e prc 1 JRC 4 pcr 1 JRZ # 1 LD 2 e prc 2 JRC 4 pcr JRZ 4 v sd 1 2 e prc 1 JRC 4 pcr 1 JRZ # 1 INC 2 e prc JRC 4 pcr JRZ 4 a,y sd 1 2 e prc 1 JRC # AND a,(x) ind ANDI a,nn imm SUB a,(x) ind SUBI a,nn imm DEC (x) ind # pcr 1 JRZ # 1 LD 2 e prc JRC 4 (x),a ind pcr JRZ 4 y sd 1 2 e prc 1 JRC pcr JRZ 4 a,x pcr 1 JRZ # 1 INC 2 e prc 2 JRC 4 sd 1 2 e prc 1 JRC 4 pcr 1 JRZ # 1 LD 2 e prc 2 JRC 4 pcr JRZ 4 x sd 1 2 e prc 1 JRC 4 4 0100 JRZ # 1 INC 2 e prc 2 JRC 4 5 0101 2 e prc 1 JRC 4 6 0110 JRC 4 a,(x) ind LDI a,nn imm CP a,(x) ind CPI a,nn imm ADD a,(x) ind ADDI a,nn imm INC (x) ind # LD 7 0111 LD LOW HI 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
Abbreviations for Addressing Modes: dir Direct sd Short Direct imm Immediate inh Inherent ext Extended b.d Bit Direct bt Bit Test pcr Program Counter Relative ind Indirect
Legend: # Indicates Illegal Instructions e 5 Bit Displacement b 3 Bit Address rr 1byte dataspace address nn 1 byte immediate data abc 12 bit address ee 8 bit Displacement
Cycle Operand Bytes Addressing Mode
2 e 1
JRC prc
Mnemonic
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Opcode Map Summary (Continued)
LOW HI 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 8 1000 JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr RNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 ext 1 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 9 1001 JP 2 A 1010 JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 B 1011 RES b0,rr b.d SET b0,rr b.d RES b4,rr b.d SET b4,rr b.d RES b2,rr b.d SET b2,rr b.d RES b6,rr b.d SET b6,rr b.d RES b1,rr b.d SET b1,rr b.d RES b5,rr b.d SET b5,rr b.d RES b3,rr b.d SET b3,rr b.d RES b7,rr b.d SET b7,rr b.d 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 pcr 1 pcr 1 JRZ 4 w,a sd 1 inh 1 LD 2 e prc 2 pcr 1 JRZ 2 pcr 1 JRZ 4 w sd 1 WAIT 2 e prc 1 JRC 4 inh 1 DEC 2 e prc 2 JRC 4 pcr 1 JRZ 2 pcr 1 JRZ 4 v,a sd 1 RET 2 e prc 1 JRC 4 pcr 1 JRZ 4 a inh 1 LD 2 e prc 2 JRC 4 pcr JRZ 4 v sd 1 RCL 2 e prc 1 JRC 4 pcr 1 JRZ # 1 DEC 2 e prc 2 JRC 4 pcr 1 JRZ 4 y,a sd 1 2 e prc 1 JRC 4 inh 1 LD 2 e prc 2 JRC 4 pcr 1 JRZ 2 pcr 1 JRZ 4 y sd 1 STOP 2 e prc 1 JRC 4 inh 1 DEC 2 e prc 2 JRC 4 pcr JRZ 4 x,a pcr 1 JRZ 2 sd 1 RETI 2 e prc 1 JRC 4 pcr 1 JRZ 4 pcr 3 JRZ 4 C 1100 JRZ 4 D 1101 LDI 2 rr,nn imm DEC x sd COM a e 1 2 e 1 2 e prc 1 JRC 4 e prc 2 JRC 4 a,rr dir ADD a,(y) ind ADD a,rr dir INC (y) ind INC rr dir LD (y),a ind LD rr,a dir AND a,(y) ind AND a,rr dir SUB a,(y) ind SUB a,rr dir DEC (y) ind DEC rr dir prc 2 JRC 4 a,(y) ind CP prc 1 JRC 4 a,rr dir CP E 1110 JRC 4 a,(y) ind LD F 1111 LD LOW HI 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
1 LD 2
Abbreviations for Addressing Modes: dir Direct sd Short Direct imm Immediate inh Inherent ext Extended b.d Bit Direct bt Bit Test pcr Program Counter Relative ind Indirect
Legend: # Indicates Illegal Instructions e 5 Bit Displacement b 3 Bit Address rr 1byte dataspace address nn 1 byte immediate data abc 12 bit address ee 8 bit Displacement
Cycle Operand Bytes Addressing Mode
2 e 1
JRC prc
Mnemonic
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6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, however it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that VI and VO be higher than VSS and lower than VDD. Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (VDD or VSS). Power Considerations.The average chip-junction temperature, Tj, in Celsius can be obtained from: Tj=TA + PD x RthJA Where:TA = Ambient Temperature. RthJA =Package thermal resistance (junction-to ambient). PD = Pint + Pport. Pint =IDD x VDD (chip internal power). Pport =Port power dissipation (determined by the user).
Symbol VDD VI VO IO IVDD IVSS Tj TSTG Supply Voltage Input Voltage Output Voltage
Parameter
Value -0.3 to 7.0 VSS - 0.3 to VDD + 0.3(1) VSS - 0.3 to VDD + 0.3(1) 10 50 50 150 -60 to 150
Unit V V V mA mA mA C C
Current Drain per Pin Excluding V DD, VSS Total Current into VDD (source) Total Current out of VSS (sink) Junction Temperature Storage Temperature
Notes: - Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. - (1) Within these limits, clamping diodes are guarantee to be not conductive. Voltages outside these limits are authorised as long as injection current is kept within the specification.
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6.2 RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Test Conditions 6 Suffix Version 1 Suffix Version 3 Suffix Version fOSC = 2MHz fosc= 8MHz VDD = 3V VDD = 4.5V, 1 & 6 Suffix VDD = 4.5V, 3 Suffix VDD = 4.5 to 5.5V Value Min. -40 0 -40 3.0 4.5 0 0 0 Typ. Max. 85 70 125 6.0 6.0 4.0 8.0 4.0 +5 -5 Unit
TA VDD fOSC IINJ+ IINJ-
Operating Temperature Operating Supply Voltage Oscillator Frequency2) Pin Injection Current (positive)
C V MHz mA mA
Pin Injection Current (negative) VDD = 4.5 to 5.5V
Notes: 1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the A/D conversion. For a -1mA injection, a maximum 10 K is recommended. 2. An oscillator frequency above 1MHz is recommended for reliable A/D results.
Figure 26. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (VDD)
Maximum FREQUENCY (MHz)
8 7 6 5 4 3 2 1 2.5
FUNCTIONALITY IS NOT GUARANTEED IN THIS AREA
1 & 6 Suffix Version
3 Suffix Version
3
3.5
4
4.5
5
5.5
6
SUPPLY VOLTAGE (VDD)
The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions.
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6.3 DC ELECTRICAL CHARACTERISTICS (TA = -40 to +125C unless otherwise specified)
Symbol Parameter Test Conditions Value Min. Typ. Max. Unit
VIL VIH
Input Low Level Voltage All Input pins Input High Level Voltage All Input pins Hysteresis Voltage (1) All Input pins Low Level Output Voltage All Output pins VDD= 5V VDD= 3V
VDD x 0.3 VDD x 0.7 0.2 0.2 0.1 0.8 0.1 0.8 1.3 4.9 3.5 40 150
V V V
VHys
VOL
VOH RPU IIL IIH
IDD
VDD= 5.0V; IOL = +10A VDD= 5.0V; IOL = + 3mA VDD= 5.0V; IOL = +10A Low Level Output Voltage VDD= 5.0V; IOL = +7mA 20 mA Sink I/O pins VDD= 5.0V; IOL = +15mA High Level Output Voltage VDD= 5.0V; IOH = -10A All Output pins VDD= 5.0V; IOH = -3.0mA All Input pins Pull-up Resistance RESET pin Input Leakage Current VIN = VSS (No Pull-Up configured) All Input pins but RESET VIN = VDD Input Leakage Current VIN = VSS RESET pin VIN = VDD Supply Current in RESET VRESET=VSS Mode fOSC=8MHz Supply Current in VDD=5.0V fINT=8MHz, TA < 85C RUN Mode (2) Supply Current in WAIT VDD=5.0V fINT=8MHz, TA < 85C Mode (3) Supply Current in STOP ILOAD=0mA Mode (3) VDD=5.0V
V
V 100 350 0.1 200 900 1.0 -30 10 3.5 6.6 1.5 20 A
-8
-16
mA mA mA A
Notes: (1) Hysteresis voltage between switching levels (2) All peripherals running (3) All peripherals in stand-by
DC ELECTRICAL CHARACTERISTICS (Cont'd) (TA = -40 to +85C unless otherwise specified)
Symbol Parameter Test Conditions Value Min. Typ. Max. Unit
VOL
VOH IDD
VDD= 5.0V; IOL = +10A VDD= 5.0V; IOL = + 5mA VDD= 5.0V; IOL = +10A Low Level Output Voltage VDD= 5.0V; IOL = +10mA 20 mA Sink I/O pins VDD= 5.0V; IOL = +20mA High Level Output Voltage VDD= 5.0V; IOH = -10A All Output pins VDD= 5.0V; IOH = -5.0mA Supply Current in STOP ILOAD=0mA Mode (3) VDD=5.0V
Low Level Output Voltage All Output pins
0.1 0.8 0.1 0.8 1.3 4.9 3.5 10
V
V A
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6.4 AC ELECTRICAL CHARACTERISTICS (TA = -40 to +125C unless otherwise specified)
Symbol tREC TWR Parameter Supply Recovery Time Minimum Pulse Width (VDD = 5V) RESET pin NMI pin EEPROM Write Time EEPROM WRITE/ERASE Cycle EEPROM Data Retention Input Capacitance Output Capacitance TA = 25C TA = 85C TA = 125C QA LOT Acceptance TA = 55C All Inputs Pins All Outputs Pins
(1)
Test Conditions
Min. 100 100 100
Value Typ.
Max.
Unit ms ns
TWEE Endurance (2) Retention CIN COUT
5 10 20 300,000 1 million 10
10 20 30
ms cycles years pF pF
10 10
Notes: 1. Period for which VDD has to be connected at 0V to allow internal Reset function at next power-up. 2. Sampled but not tested
6.5 A/D CONVERTER CHARACTERISTICS (TA = -40 to +125C unless otherwise specified)
Symbol Res ATOT tC ZIR FSR ADI ACIN Parameter Resolution Total Accuracy
(1) (2)
Test Conditions
Min.
Value Typ. 8
Max. 2 4
Unit Bit LSB s Hex
Conversion Time Zero Input Reading Full Scale Reading
fOSC > 1.2MHz fOSC > 32kHz fOSC = 8MHz, TA < 85C fOSC = 4MHz Conversion result when VIN = VSS Conversion result when VIN = VDD
70 140 00 FF 1.0 2 5
Hex A pF
Analog Input Current During VDD= 4.5V Conversion Analog Input Capacitance
Notes: 1. Noise at AVDD, AVSS <10mV 2. With oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased.
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6.6 TIMER CHARACTERISTICS (TA = -40 to +125C unless otherwise specified)
Symbol fIN tW Parameter Input Frequency on TIMER Pin Pulse Width at TIMER Pin VDD = 3.0V VDD >4.5V 1 125 Test Conditions Min. Value Typ. Max. Unit MHz s ns
fINT --------4
6.7 SPI CHARACTERISTICS (TA = -40 to +125C unless otherwise specified)
Symbol FCL tSU th Parameter Clock Frequency Set-up Time Hold Time Test Conditions Applied on Scl Applied on Sin Applied onSin Min. Value Typ. 250 50 Max. 500 Unit kHz ns ns
6.8 ARTIMER ELECTRICAL CHARACTERISTICS (TA = -40 to +125C unless otherwise specified)
Symbol Parameter Test Conditions RUN and WAIT Modes STOP mode Min Value Typ Max Unit
fIN
Input Frequency on ARTIMin Pin
fINT --------4
2
MHz
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7 GENERAL INFORMATION
7.1 PACKAGE MECHANICAL DATA Figure 27.16-Pin Plastic Dual In Line Package (B), 300-mil Width
mm Min A A1 B B1 C D D1 E E1 K1 K2 L e 2.997 3.302 3.708 .118 .130 .146 2.286 2.54 2.794 .090 .100 .110 Number of Pins Typ Max 5.08 .508 .020 .381 .508 .533 .015 .020 .021 .762 1.651 .030 .065 Min inches Typ Max .200
Dim.
.203 .254 .304 .008 .010 .012 18.92 19.18 19.56 .745 .755 .770 1.27 .050
7.37 7.62 7.874 .290 .300 .310 5.334 .210
Figure 28. 16-Pin Plastic Small Outline Package (M), 300-mil Width
mm Dim. Min A A1 B C D D1 E E1 E2 L e h alpha .102 .381 .229 10.26 10.24 7.44 .832 1.27 .508 5o Number of Pins Typ Max 2.286 .305 0.004 .483 .015 .254 .009 10.34 .404 Min Typ .090 .012 .019 .010 .407 .407 .297 .033 .050 .020 5o Max inches
10.34 .403 7.54 .293 -
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PACKAGE MECHANICAL DATA (Cont'd) THERMAL CHARACTERISTIC
Symbol RthJA Parameter Thermal Resistance Test Conditions PDIP16 PSO16 Value Min. Typ. Max. 55 75 Unit C/W
7.2 ORDERING INFORMATION Table 22. OTP/EPROM VERSION ORDERING INFORMATION
Sales Type ST62E62BF1 ST62T52BM6 ST62T52BM3 ST62T62BM6 ST62T62BM3 Program Memory (Bytes) 1836 EPROM 1836 OTP 1836 OTP EEPROM (Bytes) 64 None 64 Temperature Range 0 to +70C -40 to + 85C -40 to + 125C -40 to + 85C -40 to + 125C Package CDIP16W PSO16 PSO16
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Notes:
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ST62P52B ST62P62B
8-BIT FASTROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER AND EEPROM
s s s s s s s
s s s
s
s
s
s s s
s s s
3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data Storage in Program Memory: User selectable size Data RAM: 128 bytes Data EEPROM: 64 bytes (none on ST62T52B) 9 I/O pins, fully programmable as: - Input with pull-up resistor - Input without pull-up resistor - Input with interrupt generation - Open-drain or push-pull output - Analog Input 5 I/O lines can sink up to 20mA to drive LEDs or TRIACs directly 8-bit Timer/Counter with 7-bit programmable prescaler 8-bit Auto-reload Timer with 7-bit programmable prescaler (AR Timer) Digital Watchdog 8-bit A/D Converter with 4 analog inputs On-chip Clock oscillator can be driven by Quartz Crystal Ceramic resonator or RC network User configurable Power-on Reset One external Non-Maskable Interrupt ST626x-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port)
PDIP16
PSO16
(See end of Datasheet for Ordering Information)
DEVICE SUMMARY
DEVICE ST62P52B ST62P62B ROM
(Bytes)
EEPROM 64
1836 1836
April 1998
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1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST62P52B and ST62P62B are the Factory Advanced Service Technique ROM (FASTROM) version of ST62T52B and ST62T62B OTP devices. They offer the same functionality as OTP devices, selecting as FASTROM options the options defined in the programmable option byte of the OTP version. 1.2 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to SGS-THOMSON. 1.2.1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected FASTROM options. The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. All unused bytes must be set to FFh. The selected options are communicated to SGSTHOMSON using the correctly filled OPTION LIST appended. Table 2. FASTROM version Ordering Information
Sales Type ST62P52BM1/XXX ST62P52BM6/XXX ST62P52BM3/XXX (*) ST62P62BM1/XXX ST62P62BM6/XXX ST62P62BM3/XXX (*) (*) Advanced information ROM 1836 Bytes EEPROM (Bytes) None Temperature Range 0 to +70C -40 to + 85C -40 to + 125C 0 to +70C -40 to + 85C -40 to + 125C Package
1.2.2 Listing Generation and Verification When SGS-THOMSON receives the user's ROM contents, a computer listing is generated from it. This listing refers exactly to the ROM contents and options which will be used to produce the specified MCU. The listing is then returned to the customer who must thoroughly check, complete, sign and return it to SGS-THOMSON. The signed listing forms a part of the contractual agreement for the production of the specific customer MCU. The SGS-THOMSON Sales Organization will be pleased to provide detailed information on contractual points. Table 1. ROM Memory Map for ST62P52B/P62B
Device Address 0000h-087Fh 0880h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh Description Reserved User ROM Reserved Interrupt Vectors Reserved NMI Interrupt Vector Reset Vector
PSO16
1836 Bytes
64
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ST62P52B and ST62P62B FASTROM MICROCONTROLLER OPTION LIST Customer Address Contact Phone No Reference ..................... ..................... ..................... ..................... ..................... ..................... .... .... .... .... .... ....
SGS-THOMSON Microelectronics references Device: [ ] ST62P52B Package: [ ] Dual in Line Plastic
Temperature Range: Oscillator Source Selection: Watchdog Selection: Power on Reset Delay Readout Protection: External STOP Mode Control PB2-PB3 Pull-Up at RESET
[ ] ST62P62B [ ] Small Outline Plastic with condionning: [ ] Standard (Stick) [ ] Tape & Reel [ ] 0C to + 70C [ ] - 40C to + 85C
[ ] Crystal Quartz/Ceramic resonator [ ] RC Network [ ] Software Activation [ ] Hardware Activation [ ] 32768 cycle delay [ ] 2048 cycle delay [ ] Disabled [ ] Enabled [ ] Enabled [ ] Disabled [ ] Enabled [ ] Disabled
Comments : Supply Operating Range in the application: Oscillator Fequency in the application: Notes Signature Date ......................... ......................... .........................
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Notes:
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ST6252B ST6262B
8-BIT ROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, ROM AND EEPROM
s s s s s s s
s s s
s
s
s
s s s
s s s
3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data Storage in Program Memory: User selectable size Data RAM: 128 bytes Data EEPROM: 64 bytes (none on ST62T52B) 9 I/O pins, fully programmable as: - Input with pull-up resistor - Input without pull-up resistor - Input with interrupt generation - Open-drain or push-pull output - Analog Input 5 I/O lines can sink up to 20mA to drive LEDs or TRIACs directly 8-bit Timer/Counter with 7-bit programmable prescaler 8-bit Auto-reload Timer with 7-bit programmable prescaler (AR Timer) Digital Watchdog 8-bit A/D Converter with 4 analog inputs On-chip Clock oscillator can be driven by Quartz Crystal Ceramic resonator or RC network User configurable Power-on Reset One external Non-Maskable Interrupt ST626x-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port)
PDIP16
PSO16
(See end of Datasheet for Ordering Information)
DEVICE SUMMARY
DEVICE ST6252B ST6262B FASTROM
(Bytes)
EEPROM 64
1836 1836
April 1998
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ST6252B ST6262B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST6252B and ST6262B are mask programmed ROM version of ST62T52B and ST62T62B OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version. Figure 1. Programming wave form 1.2 ROM READOUT PROTECTION If the ROM READOUT PROTECTION option is selected, a protection fuse can be blown to prevent any access to the program memory content. In case the user wants to blow this fuse, high voltage must be applied on the TEST pin. Figure 2. Programming Circuit
TEST
0.5s min 100 s max
5V 47m F 100nF VSS VDD PROTECT TEST 100nF ZPD15 15V
VR02003
15 14V typ 10 5 t TEST 100mA max 150 s typ
14V
4mA typ
t
VR02001
Note: ZPD15 is used for overvoltage protection
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ST6252B ST6262B
ST6252B and ST6262B MICROCONTROLLER OPTION LIST Customer Address Contact Phone No Reference ..................... ..................... ..................... ..................... ..................... ..................... .... .... .... .... .... ....
SGS-THOMSON Microelectronics references Device: [ ] ST6252B Package: [ ] Dual in Line Plastic
[ ] ST6262B [ ] Small Outline Plastic with condionning: [ ] Standard (Stick) [ ] Tape & Reel Temperature Range: [ ] 0C to + 70C [ ] - 40C to + 85C Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ _ " Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character count: DIP16: 9 SO16: 5 Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator [ ] RC Network Watchdog Selection: [ ] Software Activation [ ] Hardware Activation Power on Reset Delay [ ] 32768 cycle delay [ ] 2048 cycle delay ROM Readout Protection: [ ] Disabled (Fuse cannot be blown) [ ] Enabled (Fuse can be blown by the customer) Note: No part is delivered with protected ROM. The fuse must be blown for protection to be effective. External STOP Mode Control [ ] Enabled [ ] Disabled PB2-PB3 Pull-Up at RESET [ ] Enabled [ ] Disabled Comments : Supply Operating Range in the application: Oscillator Fequency in the application: Notes Signature Date ......................... ......................... .........................
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ST6252B ST6262B
1.3 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to SGS-THOMSON. 1.3.1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected mask options. The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. All unused bytes must be set to FFh. The selected mask options are communicated to SGS-THOMSON using the correctly filled OPTION LIST appended. 1.3.2 Listing Generation and Verification When SGS-THOMSON receives the user's ROM contents, a computer listing is generated from it. This listing refers exactly to the mask which will be used to produce the specified MCU. The listing is Table 2. ROM version Ordering Information
Sales Type ST6252BB1/XXX ST6252BB6/XXX ST6252BB3/XXX ST6252BM1/XXX ST6252BM6/XXX ST6252BM3/XXX ST6262BB1/XXX ST6262BB6/XXX ST6262BB3/XXX ST6262BM1/XXX ST6262BM6/XXX ST6262BM3/XXX ROM
then returned to the customer who must thoroughly check, complete, sign and return it to SGS-THOMSON. The signed listing forms a part of the contractual agreement for the creation of the specific customer mask. The SGS-THOMSON Sales Organization will be pleased to provide detailed information on contractual points.
Table 1. ROM Memory Map for ST6252B/62B
Device Address 0000h-087Fh 0880h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh Description Reserved User ROM Reserved Interrupt Vectors Reserved NMI Interrupt Vector Reset Vector
EEPROM (Bytes)
1836 Bytes
None
1836 Bytes
64
Temperature Range 0 to +70C -40 to + 85C -40 to + 125C 0 to +70C -40 to + 85C -40 to + 125C 0 to +70C -40 to + 85C -40 to + 125C 0 to +70C -40 to + 85C -40 to + 125C
Package PDIP16
PSO16
PDIP16
PSO16
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics. (c)1998 SGS-THOMSON Microelectronics - All rights reserved. Purchase of I2C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. SGS-THOMSON Microelectronics Group of Companies Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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